s->cc_op = CC_OP_FLAGS;
}
-static inline TCGv gen_extend(TCGv val, int opsize, int sign)
+static inline TCGv gen_extend(DisasContext *s, TCGv val, int opsize, int sign)
{
TCGv tmp;
gen_partset_reg(opsize, reg, val);
return store_dummy;
} else {
- return gen_extend(reg, opsize, what == EA_LOADS);
+ return gen_extend(s, reg, opsize, what == EA_LOADS);
}
case 1: /* Address register direct. */
reg = get_areg(s, reg0);
tcg_gen_mov_i32(reg, val);
return store_dummy;
} else {
- return gen_extend(reg, opsize, what == EA_LOADS);
+ return gen_extend(s, reg, opsize, what == EA_LOADS);
}
case 2: /* Indirect register */
reg = get_areg(s, reg0);
gen_flush_flags(s); /* !Z is sticky */
- src = gen_extend(DREG(insn, 0), OS_BYTE, 0);
- dest = gen_extend(DREG(insn, 9), OS_BYTE, 0);
+ src = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
+ dest = gen_extend(s, DREG(insn, 9), OS_BYTE, 0);
bcd_add(dest, src);
gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
gen_flush_flags(s); /* !Z is sticky */
- src = gen_extend(DREG(insn, 0), OS_BYTE, 0);
- dest = gen_extend(DREG(insn, 9), OS_BYTE, 0);
+ src = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
+ dest = gen_extend(s, DREG(insn, 9), OS_BYTE, 0);
bcd_sub(dest, src);
add = (insn & 0x4000) != 0;
opsize = insn_opsize(insn);
- reg = gen_extend(DREG(insn, 9), opsize, 1);
+ reg = gen_extend(s, DREG(insn, 9), opsize, 1);
dest = tcg_temp_new();
if (insn & 0x100) {
SRC_EA(env, tmp, opsize, 1, &addr);
return;
}
- cmp = gen_extend(DREG(ext, 0), opsize, 1);
+ cmp = gen_extend(s, DREG(ext, 0), opsize, 1);
/* if <EA> == Dc then
* <EA> = Du
int opsize;
opsize = insn_opsize(insn);
- reg = gen_extend(DREG(insn, 9), opsize, 0);
+ reg = gen_extend(s, DREG(insn, 9), opsize, 0);
dest = tcg_temp_new();
if (insn & 0x100) {
SRC_EA(env, src, opsize, 0, &addr);
opsize = insn_opsize(insn);
- src = gen_extend(DREG(insn, 0), opsize, 1);
- dest = gen_extend(DREG(insn, 9), opsize, 1);
+ src = gen_extend(s, DREG(insn, 0), opsize, 1);
+ dest = gen_extend(s, DREG(insn, 9), opsize, 1);
gen_subx(s, src, dest, opsize);
opsize = insn_opsize(insn);
SRC_EA(env, src, opsize, 1, NULL);
- reg = gen_extend(DREG(insn, 9), opsize, 1);
+ reg = gen_extend(s, DREG(insn, 9), opsize, 1);
gen_update_cc_cmp(s, reg, src, opsize);
}
opsize = insn_opsize(insn);
- dest = gen_extend(DREG(insn, 9), opsize, 1);
- src = gen_extend(DREG(insn, 0), opsize, 1);
+ dest = gen_extend(s, DREG(insn, 9), opsize, 1);
+ src = gen_extend(s, DREG(insn, 0), opsize, 1);
gen_addx(s, src, dest, opsize);
int logical = insn & 8;
int left = insn & 0x100;
int bits = opsize_bytes(opsize) * 8;
- TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical);
+ TCGv reg = gen_extend(s, DREG(insn, 0), opsize, !logical);
if (count == 0) {
count = 8;
int logical = insn & 8;
int left = insn & 0x100;
int bits = opsize_bytes(opsize) * 8;
- TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical);
+ TCGv reg = gen_extend(s, DREG(insn, 0), opsize, !logical);
TCGv s32;
TCGv_i64 t64, s64;
while M68000 sets if the most significant bit is changed at
any time during the shift operation */
if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
- src = gen_extend(src, OS_WORD, 1);
+ src = gen_extend(s, src, OS_WORD, 1);
tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
}
} else {
TCGv shift;
int tmp;
- reg = gen_extend(DREG(insn, 0), OS_BYTE, 0);
+ reg = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
tmp = (insn >> 9) & 7;
if (tmp == 0) {
TCGv shift;
int tmp;
- reg = gen_extend(DREG(insn, 0), OS_WORD, 0);
+ reg = gen_extend(s, DREG(insn, 0), OS_WORD, 0);
tmp = (insn >> 9) & 7;
if (tmp == 0) {
tmp = 8;
TCGv t0, t1;
int left = (insn & 0x100);
- reg = gen_extend(DREG(insn, 0), OS_BYTE, 0);
+ reg = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
src = DREG(insn, 9);
/* shift in [0..63] */
t0 = tcg_temp_new_i32();
TCGv t0, t1;
int left = (insn & 0x100);
- reg = gen_extend(DREG(insn, 0), OS_WORD, 0);
+ reg = gen_extend(s, DREG(insn, 0), OS_WORD, 0);
src = DREG(insn, 9);
/* shift in [0..63] */
t0 = tcg_temp_new_i32();
return;
}
SRC_EA(env, src, opsize, 1, NULL);
- reg = gen_extend(DREG(insn, 9), opsize, 1);
+ reg = gen_extend(s, DREG(insn, 9), opsize, 1);
gen_flush_flags(s);
gen_helper_chk(cpu_env, reg, src);