drm/i915/gt: One more flush for Baytrail clear residuals

commit e627d5923cae93fa4188f4c4afba6486169a1337 upstream.

CI reports that Baytail requires one more invalidate after CACHE_MODE
for it to be happy.

Fixes: ace44e13e577 ("drm/i915/gt: Clear CACHE_MODE prior to clearing residuals")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Diego Calleja <diegocg@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210119110802.22228-1-chris@chris-wilson.co.uk
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Andrea Righi <andrea.righi@canonical.com>

diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
index e961ad6a312944a89c09adcd5c57e29466d7e43d..c50b18dd67be126dcbc4fe676ef845f9c85f92f9 100644 (file)
--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
@@ -353,19 +353,21 @@ static void gen7_emit_pipeline_flush(struct batch_chunk *batch)
 
 static void gen7_emit_pipeline_invalidate(struct batch_chunk *batch)
 {
-       u32 *cs = batch_alloc_items(batch, 0, 8);
+       u32 *cs = batch_alloc_items(batch, 0, 10);
 
        /* ivb: Stall before STATE_CACHE_INVALIDATE */
-       *cs++ = GFX_OP_PIPE_CONTROL(4);
+       *cs++ = GFX_OP_PIPE_CONTROL(5);
        *cs++ = PIPE_CONTROL_STALL_AT_SCOREBOARD |
                PIPE_CONTROL_CS_STALL;
        *cs++ = 0;
        *cs++ = 0;
+       *cs++ = 0;
 
-       *cs++ = GFX_OP_PIPE_CONTROL(4);
+       *cs++ = GFX_OP_PIPE_CONTROL(5);
        *cs++ = PIPE_CONTROL_STATE_CACHE_INVALIDATE;
        *cs++ = 0;
        *cs++ = 0;
+       *cs++ = 0;
 
        batch_advance(batch, cs);
 }
@@ -397,6 +399,7 @@ static void emit_batch(struct i915_vma * const vma,
        batch_add(&cmds, 0xffff0000);
        batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1));
        batch_add(&cmds, 0xffff0000 | PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
+       gen7_emit_pipeline_invalidate(&cmds);
        gen7_emit_pipeline_flush(&cmds);
 
        /* Switch to the media pipeline and our base address */