pwm: meson: Consider 128 a valid pre-divider

BugLink: https://bugs.launchpad.net/bugs/1863019
[ Upstream commit 51496e4446875726d50a5617a6e0e0dabbc2e6da ]

The pre-divider allows configuring longer PWM periods compared to using
the input clock directly. The pre-divider is 7 bit wide, meaning it's
maximum value is 128 (the register value is off-by-one: 0x7f or 127).

Change the loop to also allow for the maximum possible value to be
considered valid.

Fixes: 211ed630753d2f ("pwm: Add support for Meson PWM Controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Khalid Elmously <khalid.elmously@canonical.com>

diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
index 9b79cbc7a7152a0ae01d814d96d8c7b0c034c684..9551f896dd6f38b170f72840c7dd33c7d335106c 100644 (file)
--- a/drivers/pwm/pwm-meson.c
+++ b/drivers/pwm/pwm-meson.c
@@ -188,7 +188,7 @@ static int meson_pwm_calc(struct meson_pwm *meson,
        do_div(fin_ps, fin_freq);
 
        /* Calc pre_div with the period */
-       for (pre_div = 0; pre_div < MISC_CLK_DIV_MASK; pre_div++) {
+       for (pre_div = 0; pre_div <= MISC_CLK_DIV_MASK; pre_div++) {
                cnt = DIV_ROUND_CLOSEST_ULL((u64)period * 1000,
                                            fin_ps * (pre_div + 1));
                dev_dbg(meson->chip.dev, "fin_ps=%llu pre_div=%u cnt=%u\n",
@@ -197,7 +197,7 @@ static int meson_pwm_calc(struct meson_pwm *meson,
                        break;
        }
 
-       if (pre_div == MISC_CLK_DIV_MASK) {
+       if (pre_div > MISC_CLK_DIV_MASK) {
                dev_err(meson->chip.dev, "unable to get period pre_div\n");
                return -EINVAL;
        }