drm/nouveau/kms/nv50-: Use downstream DP clock limits for mode validation

This adds support for querying the maximum clock rate of a downstream
port on a DisplayPort connection. Generally, downstream ports refer to
active dongles which can have their own pixel clock limits.

Note as well, we also start marking the connector as disconnected if we
can't read the DPCD, since we wouldn't be able to do anything without
DPCD access anyway.

Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200826182456.322681-15-lyude@redhat.com

diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 8e1effb10425d32054abe8b84016f36761752aff..d2141ca16107bc8a0921cf1b467ca46dbc29ca64 100644 (file)
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -1258,7 +1258,10 @@ nv50_mstc_detect(struct drm_connector *connector,
 
        ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
                                     mstc->port);
+       if (ret != connector_status_connected)
+               goto out;
 
+out:
        pm_runtime_mark_last_busy(connector->dev->dev);
        pm_runtime_put_autosuspend(connector->dev->dev);
        return ret;

diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c
index 005750aeb6d4f0e4e2754a0c92e7fefe9517d75f..ad852e572cfec4a5791be2146c5b35bbd2c9de29 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_dp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dp.c
@@ -61,6 +61,11 @@ nouveau_dp_probe_dpcd(struct nouveau_connector *nv_connector,
                        mstm->can_mst = drm_dp_read_mst_cap(aux, dpcd);
        }
 
+       ret = drm_dp_read_downstream_info(aux, dpcd,
+                                         outp->dp.downstream_ports);
+       if (ret < 0)
+               return connector_status_disconnected;
+
        return connector_status_connected;
 }
 
@@ -176,8 +181,6 @@ void nouveau_dp_irq(struct nouveau_drm *drm,
 /* TODO:
  * - Use the minimum possible BPC here, once we add support for the max bpc
  *   property.
- * - Validate the mode against downstream port caps (see
- *   drm_dp_downstream_max_clock())
  * - Validate against the DP caps advertised by the GPU (we don't check these
  *   yet)
  */
@@ -188,15 +191,19 @@ nv50_dp_mode_valid(struct drm_connector *connector,
                   unsigned *out_clock)
 {
        const unsigned min_clock = 25000;
-       unsigned max_clock, clock;
+       unsigned max_clock, ds_clock, clock;
        enum drm_mode_status ret;
 
        if (mode->flags & DRM_MODE_FLAG_INTERLACE && !outp->caps.dp_interlace)
                return MODE_NO_INTERLACE;
 
        max_clock = outp->dp.link_nr * outp->dp.link_bw;
-       clock = mode->clock * (connector->display_info.bpc * 3) / 10;
+       ds_clock = drm_dp_downstream_max_clock(outp->dp.dpcd,
+                                              outp->dp.downstream_ports);
+       if (ds_clock)
+               max_clock = min(max_clock, ds_clock);
 
+       clock = mode->clock * (connector->display_info.bpc * 3) / 10;
        ret = nouveau_conn_mode_clock_valid(mode, min_clock, max_clock,
                                            &clock);
        if (out_clock)

diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h
index eef4643f5f9820e511af8ff56141c9563dda132b..c1924a4529a7b1602c19e0c835a17d07f169738d 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_encoder.h
+++ b/drivers/gpu/drm/nouveau/nouveau_encoder.h
@@ -72,6 +72,7 @@ struct nouveau_encoder {
                        struct mutex hpd_irq_lock;
 
                        u8 dpcd[DP_RECEIVER_CAP_SIZE];
+                       u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
                        struct drm_dp_desc desc;
                } dp;
        };