dt-bindings: clk: axg-audio-clkc: expose all clock ids

Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.

This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.

It was decided to move every axg-audio-clkc ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.

[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-14-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h
index d6ed27c777292a1980ccc749accee3da2dd4a14c..faf08748b20500f6179234bb5d9802706861b815 100644 (file)
--- a/drivers/clk/meson/axg-audio.h
+++ b/drivers/clk/meson/axg-audio.h
@@ -64,76 +64,6 @@
 #define AUDIO_SM1_SW_RESET1    0x02C
 #define AUDIO_CLK81_CTRL       0x030
 #define AUDIO_CLK81_EN         0x034
-/*
- * CLKID index values
- * These indices are entirely contrived and do not map onto the hardware.
- */
-
-#define AUD_CLKID_MST_A_MCLK_SEL       59
-#define AUD_CLKID_MST_B_MCLK_SEL       60
-#define AUD_CLKID_MST_C_MCLK_SEL       61
-#define AUD_CLKID_MST_D_MCLK_SEL       62
-#define AUD_CLKID_MST_E_MCLK_SEL       63
-#define AUD_CLKID_MST_F_MCLK_SEL       64
-#define AUD_CLKID_MST_A_MCLK_DIV       65
-#define AUD_CLKID_MST_B_MCLK_DIV       66
-#define AUD_CLKID_MST_C_MCLK_DIV       67
-#define AUD_CLKID_MST_D_MCLK_DIV       68
-#define AUD_CLKID_MST_E_MCLK_DIV       69
-#define AUD_CLKID_MST_F_MCLK_DIV       70
-#define AUD_CLKID_SPDIFOUT_CLK_SEL     71
-#define AUD_CLKID_SPDIFOUT_CLK_DIV     72
-#define AUD_CLKID_SPDIFIN_CLK_SEL      73
-#define AUD_CLKID_SPDIFIN_CLK_DIV      74
-#define AUD_CLKID_PDM_DCLK_SEL         75
-#define AUD_CLKID_PDM_DCLK_DIV         76
-#define AUD_CLKID_PDM_SYSCLK_SEL       77
-#define AUD_CLKID_PDM_SYSCLK_DIV       78
-#define AUD_CLKID_MST_A_SCLK_PRE_EN    92
-#define AUD_CLKID_MST_B_SCLK_PRE_EN    93
-#define AUD_CLKID_MST_C_SCLK_PRE_EN    94
-#define AUD_CLKID_MST_D_SCLK_PRE_EN    95
-#define AUD_CLKID_MST_E_SCLK_PRE_EN    96
-#define AUD_CLKID_MST_F_SCLK_PRE_EN    97
-#define AUD_CLKID_MST_A_SCLK_DIV       98
-#define AUD_CLKID_MST_B_SCLK_DIV       99
-#define AUD_CLKID_MST_C_SCLK_DIV       100
-#define AUD_CLKID_MST_D_SCLK_DIV       101
-#define AUD_CLKID_MST_E_SCLK_DIV       102
-#define AUD_CLKID_MST_F_SCLK_DIV       103
-#define AUD_CLKID_MST_A_SCLK_POST_EN   104
-#define AUD_CLKID_MST_B_SCLK_POST_EN   105
-#define AUD_CLKID_MST_C_SCLK_POST_EN   106
-#define AUD_CLKID_MST_D_SCLK_POST_EN   107
-#define AUD_CLKID_MST_E_SCLK_POST_EN   108
-#define AUD_CLKID_MST_F_SCLK_POST_EN   109
-#define AUD_CLKID_MST_A_LRCLK_DIV      110
-#define AUD_CLKID_MST_B_LRCLK_DIV      111
-#define AUD_CLKID_MST_C_LRCLK_DIV      112
-#define AUD_CLKID_MST_D_LRCLK_DIV      113
-#define AUD_CLKID_MST_E_LRCLK_DIV      114
-#define AUD_CLKID_MST_F_LRCLK_DIV      115
-#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN  137
-#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN  138
-#define AUD_CLKID_TDMIN_C_SCLK_PRE_EN  139
-#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 140
-#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 141
-#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 142
-#define AUD_CLKID_TDMOUT_C_SCLK_PRE_EN 143
-#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 144
-#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 145
-#define AUD_CLKID_TDMIN_C_SCLK_POST_EN 146
-#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN        147
-#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN        148
-#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN        149
-#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN        150
-#define AUD_CLKID_SPDIFOUT_B_CLK_SEL   153
-#define AUD_CLKID_SPDIFOUT_B_CLK_DIV   154
-#define AUD_CLKID_CLK81_EN             173
-#define AUD_CLKID_SYSCLK_A_DIV         174
-#define AUD_CLKID_SYSCLK_B_DIV         175
-#define AUD_CLKID_SYSCLK_A_EN          176
-#define AUD_CLKID_SYSCLK_B_EN          177
 
 /* include the CLKIDs which are part of the DT bindings */
 #include <dt-bindings/clock/axg-audio-clkc.h>

diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h
index f561f5c5ef8f281a23bced0b79ca4a026cbf8eed..08c82c22fa5f983456dde22891bccb535303f77d 100644 (file)
--- a/include/dt-bindings/clock/axg-audio-clkc.h
+++ b/include/dt-bindings/clock/axg-audio-clkc.h
@@ -37,6 +37,26 @@
 #define AUD_CLKID_SPDIFIN_CLK          56
 #define AUD_CLKID_PDM_DCLK             57
 #define AUD_CLKID_PDM_SYSCLK           58
+#define AUD_CLKID_MST_A_MCLK_SEL       59
+#define AUD_CLKID_MST_B_MCLK_SEL       60
+#define AUD_CLKID_MST_C_MCLK_SEL       61
+#define AUD_CLKID_MST_D_MCLK_SEL       62
+#define AUD_CLKID_MST_E_MCLK_SEL       63
+#define AUD_CLKID_MST_F_MCLK_SEL       64
+#define AUD_CLKID_MST_A_MCLK_DIV       65
+#define AUD_CLKID_MST_B_MCLK_DIV       66
+#define AUD_CLKID_MST_C_MCLK_DIV       67
+#define AUD_CLKID_MST_D_MCLK_DIV       68
+#define AUD_CLKID_MST_E_MCLK_DIV       69
+#define AUD_CLKID_MST_F_MCLK_DIV       70
+#define AUD_CLKID_SPDIFOUT_CLK_SEL     71
+#define AUD_CLKID_SPDIFOUT_CLK_DIV     72
+#define AUD_CLKID_SPDIFIN_CLK_SEL      73
+#define AUD_CLKID_SPDIFIN_CLK_DIV      74
+#define AUD_CLKID_PDM_DCLK_SEL         75
+#define AUD_CLKID_PDM_DCLK_DIV         76
+#define AUD_CLKID_PDM_SYSCLK_SEL       77
+#define AUD_CLKID_PDM_SYSCLK_DIV       78
 #define AUD_CLKID_MST_A_SCLK           79
 #define AUD_CLKID_MST_B_SCLK           80
 #define AUD_CLKID_MST_C_SCLK           81
@@ -49,6 +69,30 @@
 #define AUD_CLKID_MST_D_LRCLK          89
 #define AUD_CLKID_MST_E_LRCLK          90
 #define AUD_CLKID_MST_F_LRCLK          91
+#define AUD_CLKID_MST_A_SCLK_PRE_EN    92
+#define AUD_CLKID_MST_B_SCLK_PRE_EN    93
+#define AUD_CLKID_MST_C_SCLK_PRE_EN    94
+#define AUD_CLKID_MST_D_SCLK_PRE_EN    95
+#define AUD_CLKID_MST_E_SCLK_PRE_EN    96
+#define AUD_CLKID_MST_F_SCLK_PRE_EN    97
+#define AUD_CLKID_MST_A_SCLK_DIV       98
+#define AUD_CLKID_MST_B_SCLK_DIV       99
+#define AUD_CLKID_MST_C_SCLK_DIV       100
+#define AUD_CLKID_MST_D_SCLK_DIV       101
+#define AUD_CLKID_MST_E_SCLK_DIV       102
+#define AUD_CLKID_MST_F_SCLK_DIV       103
+#define AUD_CLKID_MST_A_SCLK_POST_EN   104
+#define AUD_CLKID_MST_B_SCLK_POST_EN   105
+#define AUD_CLKID_MST_C_SCLK_POST_EN   106
+#define AUD_CLKID_MST_D_SCLK_POST_EN   107
+#define AUD_CLKID_MST_E_SCLK_POST_EN   108
+#define AUD_CLKID_MST_F_SCLK_POST_EN   109
+#define AUD_CLKID_MST_A_LRCLK_DIV      110
+#define AUD_CLKID_MST_B_LRCLK_DIV      111
+#define AUD_CLKID_MST_C_LRCLK_DIV      112
+#define AUD_CLKID_MST_D_LRCLK_DIV      113
+#define AUD_CLKID_MST_E_LRCLK_DIV      114
+#define AUD_CLKID_MST_F_LRCLK_DIV      115
 #define AUD_CLKID_TDMIN_A_SCLK_SEL     116
 #define AUD_CLKID_TDMIN_B_SCLK_SEL     117
 #define AUD_CLKID_TDMIN_C_SCLK_SEL     118
@@ -70,8 +114,24 @@
 #define AUD_CLKID_TDMOUT_A_LRCLK       134
 #define AUD_CLKID_TDMOUT_B_LRCLK       135
 #define AUD_CLKID_TDMOUT_C_LRCLK       136
+#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN  137
+#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN  138
+#define AUD_CLKID_TDMIN_C_SCLK_PRE_EN  139
+#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 140
+#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 141
+#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 142
+#define AUD_CLKID_TDMOUT_C_SCLK_PRE_EN 143
+#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 144
+#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 145
+#define AUD_CLKID_TDMIN_C_SCLK_POST_EN 146
+#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN        147
+#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN        148
+#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN        149
+#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN        150
 #define AUD_CLKID_SPDIFOUT_B           151
 #define AUD_CLKID_SPDIFOUT_B_CLK       152
+#define AUD_CLKID_SPDIFOUT_B_CLK_SEL   153
+#define AUD_CLKID_SPDIFOUT_B_CLK_DIV   154
 #define AUD_CLKID_TDM_MCLK_PAD0                155
 #define AUD_CLKID_TDM_MCLK_PAD1                156
 #define AUD_CLKID_TDM_LRCLK_PAD0       157
@@ -90,5 +150,10 @@
 #define AUD_CLKID_FRDDR_D              170
 #define AUD_CLKID_TODDR_D              171
 #define AUD_CLKID_LOOPBACK_B           172
+#define AUD_CLKID_CLK81_EN             173
+#define AUD_CLKID_SYSCLK_A_DIV         174
+#define AUD_CLKID_SYSCLK_B_DIV         175
+#define AUD_CLKID_SYSCLK_A_EN          176
+#define AUD_CLKID_SYSCLK_B_EN          177
 
 #endif /* __AXG_AUDIO_CLKC_BINDINGS_H */