if (dpi_use_dsi_pll(dssdev)) {
dss_clk_enable(DSS_CLK_SYSCK);
- r = dsi_pll_init(dssdev, 0, 1);
+ r = dsi_pll_init(0, 1);
if (r)
goto err3;
}
return r;
}
-int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
- bool enable_hsdiv)
+int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv)
{
int r = 0;
enum dsi_pll_power_state pwstate;
{
int r;
- r = dsi_pll_init(dssdev, true, true);
+ r = dsi_pll_init(true, true);
if (r)
goto err0;
int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
struct dsi_clock_info *cinfo,
struct dispc_clock_info *dispc_cinfo);
-int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
- bool enable_hsdiv);
+int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv);
void dsi_pll_uninit(bool disconnect_lanes);
void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
u32 fifo_size, enum omap_burst_size *burst_size,