drm/amd/powerplay: remove SRIOV check in SMU11 (v2)

We don't need SRIOV check after we enable SMC msg filter in SMU11

v2: squash in unused variable fix, unused ids

Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index f7428996cc7417ce79fbd97b577c6760a5d0417f..a70282d439ba47c7cefbd7993a88255d8a68dbc4 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -563,10 +563,8 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int
 
 bool is_support_sw_smu(struct amdgpu_device *adev)
 {
-       if (adev->asic_type >= CHIP_ARCTURUS) {
-             if (amdgpu_sriov_is_pp_one_vf(adev) || !amdgpu_sriov_vf(adev))
-                       return true;
-       }
+       if (adev->asic_type >= CHIP_ARCTURUS)
+               return true;
 
        return false;
 }
@@ -1109,59 +1107,54 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
                return ret;
 
        /* smu_dump_pptable(smu); */
-       if (!amdgpu_sriov_vf(adev)) {
-               /*
-                * Copy pptable bo in the vram to smc with SMU MSGs such as
-                * SetDriverDramAddr and TransferTableDram2Smu.
-                */
-               ret = smu_write_pptable(smu);
-               if (ret)
-                       return ret;
-
-               /* issue Run*Btc msg */
-               ret = smu_run_btc(smu);
-               if (ret)
-                       return ret;
-               ret = smu_feature_set_allowed_mask(smu);
-               if (ret)
-                       return ret;
+       /*
+        * Copy pptable bo in the vram to smc with SMU MSGs such as
+        * SetDriverDramAddr and TransferTableDram2Smu.
+        */
+       ret = smu_write_pptable(smu);
+       if (ret)
+               return ret;
 
-               ret = smu_system_features_control(smu, true);
-               if (ret)
-                       return ret;
+       /* issue Run*Btc msg */
+       ret = smu_run_btc(smu);
+       if (ret)
+               return ret;
+       ret = smu_feature_set_allowed_mask(smu);
+       if (ret)
+               return ret;
 
-               if (adev->asic_type == CHIP_NAVI10) {
-                       if ((adev->pdev->device == 0x731f && (adev->pdev->revision == 0xc2 ||
-                                                             adev->pdev->revision == 0xc3 ||
-                                                             adev->pdev->revision == 0xca ||
-                                                             adev->pdev->revision == 0xcb)) ||
-                           (adev->pdev->device == 0x66af && (adev->pdev->revision == 0xf3 ||
-                                                             adev->pdev->revision == 0xf4 ||
-                                                             adev->pdev->revision == 0xf5 ||
-                                                             adev->pdev->revision == 0xf6))) {
-                               ret = smu_disable_umc_cdr_12gbps_workaround(smu);
-                               if (ret) {
-                                       pr_err("Workaround failed to disable UMC CDR feature on 12Gbps SKU!\n");
-                                       return ret;
-                               }
-                       }
-               }
+       ret = smu_system_features_control(smu, true);
+       if (ret)
+               return ret;
 
-               if (smu->ppt_funcs->set_power_source) {
-                       /*
-                        * For Navi1X, manually switch it to AC mode as PMFW
-                        * may boot it with DC mode.
-                        */
-                       if (adev->pm.ac_power)
-                               ret = smu_set_power_source(smu, SMU_POWER_SOURCE_AC);
-                       else
-                               ret = smu_set_power_source(smu, SMU_POWER_SOURCE_DC);
+       if (adev->asic_type == CHIP_NAVI10) {
+               if (adev->pdev->device == 0x731f && (adev->pdev->revision == 0xc2 ||
+                                                    adev->pdev->revision == 0xc3 ||
+                                                    adev->pdev->revision == 0xca ||
+                                                    adev->pdev->revision == 0xcb)) {
+                       ret = smu_disable_umc_cdr_12gbps_workaround(smu);
                        if (ret) {
-                               pr_err("Failed to switch to %s mode!\n", adev->pm.ac_power ? "AC" : "DC");
+                               pr_err("Workaround failed to disable UMC CDR feature on 12Gbps SKU!\n");
                                return ret;
                        }
                }
        }
+
+       if (smu->ppt_funcs->set_power_source) {
+               /*
+                * For Navi1X, manually switch it to AC mode as PMFW
+                * may boot it with DC mode.
+                */
+               if (adev->pm.ac_power)
+                       ret = smu_set_power_source(smu, SMU_POWER_SOURCE_AC);
+               else
+                       ret = smu_set_power_source(smu, SMU_POWER_SOURCE_DC);
+               if (ret) {
+                       pr_err("Failed to switch to %s mode!\n", adev->pm.ac_power ? "AC" : "DC");
+                       return ret;
+               }
+       }
+
        if (adev->asic_type != CHIP_ARCTURUS) {
                ret = smu_notify_display_change(smu);
                if (ret)
@@ -1214,9 +1207,8 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
        /*
         * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
         */
-       if (!amdgpu_sriov_vf(adev)) {
-               ret = smu_set_tool_table_location(smu);
-       }
+       ret = smu_set_tool_table_location(smu);
+
        if (!smu_is_dpm_running(smu))
                pr_info("dpm has been disabled\n");
 
@@ -1376,9 +1368,6 @@ failed:
 
 static int smu_stop_dpms(struct smu_context *smu)
 {
-       if (amdgpu_sriov_vf(smu->adev))
-               return 0;
-
        return smu_system_features_control(smu, false);
 }
 
@@ -1403,35 +1392,35 @@ static int smu_hw_fini(void *handle)
 
        adev->pm.dpm_enabled = false;
 
-       if (!amdgpu_sriov_vf(adev)){
+       if (!amdgpu_sriov_vf(adev)) {
                smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);
+       }
+
+       ret = smu_stop_thermal_control(smu);
+       if (ret) {
+               pr_warn("Fail to stop thermal control!\n");
+               return ret;
+       }
 
-               ret = smu_stop_thermal_control(smu);
+       /*
+        * For custom pptable uploading, skip the DPM features
+        * disable process on Navi1x ASICs.
+        *   - As the gfx related features are under control of
+        *     RLC on those ASICs. RLC reinitialization will be
+        *     needed to reenable them. That will cost much more
+        *     efforts.
+        *
+        *   - SMU firmware can handle the DPM reenablement
+        *     properly.
+        */
+       if (!smu->uploading_custom_pp_table ||
+                       !((adev->asic_type >= CHIP_NAVI10) &&
+                               (adev->asic_type <= CHIP_NAVI12))) {
+               ret = smu_stop_dpms(smu);
                if (ret) {
-                       pr_warn("Fail to stop thermal control!\n");
+                       pr_warn("Fail to stop Dpms!\n");
                        return ret;
                }
-
-               /*
-                * For custom pptable uploading, skip the DPM features
-                * disable process on Navi1x ASICs.
-                *   - As the gfx related features are under control of
-                *     RLC on those ASICs. RLC reinitialization will be
-                *     needed to reenable them. That will cost much more
-                *     efforts.
-                *
-                *   - SMU firmware can handle the DPM reenablement
-                *     properly.
-                */
-               if (!smu->uploading_custom_pp_table ||
-                               !((adev->asic_type >= CHIP_NAVI10) &&
-                                       (adev->asic_type <= CHIP_NAVI12))) {
-                       ret = smu_stop_dpms(smu);
-                       if (ret) {
-                               pr_warn("Fail to stop Dpms!\n");
-                               return ret;
-                       }
-               }
        }
 
        kfree(table_context->driver_pptable);
@@ -1548,12 +1537,12 @@ static int smu_suspend(void *handle)
 
        if (!amdgpu_sriov_vf(adev)) {
                smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);
-
-               ret = smu_disable_dpm(smu);
-               if (ret)
-                       return ret;
        }
 
+       ret = smu_disable_dpm(smu);
+       if (ret)
+               return ret;
+
        smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
 
        if (adev->asic_type >= CHIP_NAVI10 &&

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index dcbb273674d143ac60e66809b3eecbc5f75ce1b0..0b12a5c706edbb3ae04c7fe3331f186e263d9df4 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -1335,7 +1335,6 @@ static int arcturus_get_power_limit(struct smu_context *smu,
 static int arcturus_get_power_profile_mode(struct smu_context *smu,
                                           char *buf)
 {
-       struct amdgpu_device *adev = smu->adev;
        DpmActivityMonitorCoeffInt_t activity_monitor;
        static const char *profile_name[] = {
                                        "BOOTUP_DEFAULT",
@@ -1369,7 +1368,7 @@ static int arcturus_get_power_profile_mode(struct smu_context *smu,
        if (result)
                return result;
 
-       if (smu_version >= 0x360d00 && !amdgpu_sriov_vf(adev))
+       if (smu_version >= 0x360d00)
                size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
                        title[0], title[1], title[2], title[3], title[4], title[5],
                        title[6], title[7], title[8], title[9], title[10]);
@@ -1386,7 +1385,7 @@ static int arcturus_get_power_profile_mode(struct smu_context *smu,
                if (workload_type < 0)
                        continue;
 
-               if (smu_version >= 0x360d00 && !amdgpu_sriov_vf(adev)) {
+               if (smu_version >= 0x360d00) {
                        result = smu_update_table(smu,
                                                  SMU_TABLE_ACTIVITY_MONITOR_COEFF,
                                                  workload_type,
@@ -1401,7 +1400,7 @@ static int arcturus_get_power_profile_mode(struct smu_context *smu,
                size += sprintf(buf + size, "%2d %14s%s\n",
                        i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
 
-               if (smu_version >= 0x360d00 && !amdgpu_sriov_vf(adev)) {
+               if (smu_version >= 0x360d00) {
                        size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
                                " ",
                                0,

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 5f7373e86d90ed2f99fd20126c439bbe4f6386a1..ef4952afb3650d72dc5a0cc1e64e335f51d2f127 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1818,8 +1818,7 @@ static int navi10_get_power_limit(struct smu_context *smu,
        int power_src;
 
        if (!smu->power_limit) {
-               if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT) &&
-                       !amdgpu_sriov_vf(smu->adev)) {
+               if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
                        power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
                        if (power_src < 0)
                                return -EINVAL;
@@ -1962,9 +1961,6 @@ static int navi10_set_default_od_settings(struct smu_context *smu, bool initiali
        OverDriveTable_t *od_table, *boot_od_table;
        int ret = 0;
 
-       if (amdgpu_sriov_vf(smu->adev))
-               return 0;
-
        ret = smu_v11_0_set_default_od_settings(smu, initialize, sizeof(OverDriveTable_t));
        if (ret)
                return ret;

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index ddd03289d50ebfbd3867048a76602e2be6d5610b..b816c839cb7767870491a548696ef26b535e277f 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -768,9 +768,6 @@ int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 {
        int ret;
 
-       if (amdgpu_sriov_vf(smu->adev))
-               return 0;
-
        ret = smu_send_smc_msg_with_param(smu,
                                          SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
        if (ret)
@@ -814,9 +811,6 @@ int smu_v11_0_set_tool_table_location(struct smu_context *smu)
        int ret = 0;
        struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 
-       if (amdgpu_sriov_vf(smu->adev))
-               return 0;
-
        if (tool_table->mc_address) {
                ret = smu_send_smc_msg_with_param(smu,
                                SMU_MSG_SetToolsDramAddrHigh,
@@ -836,9 +830,6 @@ int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 {
        int ret = 0;
 
-       if (amdgpu_sriov_vf(smu->adev))
-               return 0;
-
        if (!smu->pm_enabled)
                return ret;
 
@@ -853,9 +844,6 @@ int smu_v11_0_set_allowed_mask(struct smu_context *smu)
        int ret = 0;
        uint32_t feature_mask[2];
 
-       if (amdgpu_sriov_vf(smu->adev))
-               return 0;
-
        mutex_lock(&feature->mutex);
        if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
                goto failed;
@@ -884,9 +872,6 @@ int smu_v11_0_get_enabled_mask(struct smu_context *smu,
        struct smu_feature *feature = &smu->smu_feature;
        int ret = 0;
 
-       if (amdgpu_sriov_vf(smu->adev) && !amdgpu_sriov_is_pp_one_vf(smu->adev))
-               return 0;
-
        if (!feature_mask || num < 2)
                return -EINVAL;
 
@@ -942,9 +927,6 @@ int smu_v11_0_notify_display_change(struct smu_context *smu)
 {
        int ret = 0;
 
-       if (amdgpu_sriov_vf(smu->adev))
-               return 0;
-
        if (!smu->pm_enabled)
                return ret;
 
@@ -1107,9 +1089,6 @@ int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
        int ret = 0;
        uint32_t max_power_limit;
 
-       if (amdgpu_sriov_vf(smu->adev))
-               return 0;
-
        max_power_limit = smu_v11_0_get_max_power_limit(smu);
 
        if (n > max_power_limit) {
@@ -1866,9 +1845,6 @@ int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
        uint32_t pcie_gen = 0, pcie_width = 0;
        int ret;
 
-       if (amdgpu_sriov_vf(smu->adev))
-               return 0;
-
        if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
                pcie_gen = 3;
        else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)