]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/commitdiff
drm/amdgpu/display: remove DRM_AMD_DC_GREEN_SARDINE
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 16 Oct 2020 14:25:45 +0000 (10:25 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 4 Nov 2020 13:43:50 +0000 (08:43 -0500)
No need for a separate config option at this point.

Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/Kconfig
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
drivers/gpu/drm/amd/display/include/dal_asic_id.h

index 2a30a9bd178cab36c6060f76185cc7e83841f6c3..60dfdd432aba0ed47e723d259e6313a5dad4557a 100644 (file)
@@ -17,14 +17,6 @@ config DRM_AMD_DC_DCN
        help
          Raven, Navi and Renoir family support for display engine
 
-config DRM_AMD_DC_GREEN_SARDINE
-       bool "Green Sardine support"
-       default y
-       depends on DRM_AMD_DC_DCN
-        help
-            Choose this option if you want to have
-            Green Sardine support for display engine
-
 config DRM_AMD_DC_DCN3_0
         bool "DCN 3.0 family"
         depends on DRM_AMD_DC && X86
index ad853dc7993ac94794ce90e974ca326cf61f97b9..f994d97202fe15f4882a61aa0931cd54e088d110 100644 (file)
@@ -100,10 +100,8 @@ MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 #endif
-#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
-#endif
 
 #define FIRMWARE_RAVEN_DMCU            "amdgpu/raven_dmcu.bin"
 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
@@ -977,10 +975,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
        case CHIP_RAVEN:
        case CHIP_RENOIR:
                init_data.flags.gpu_vm_support = true;
-#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
                if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
                        init_data.flags.disable_dmcu = true;
-#endif
                break;
        default:
                break;
@@ -1275,10 +1271,8 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
        case CHIP_RENOIR:
                dmub_asic = DMUB_ASIC_DCN21;
                fw_name_dmub = FIRMWARE_RENOIR_DMUB;
-#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
                if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
                        fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
-#endif
                break;
 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
        case CHIP_SIENNA_CICHLID:
index 7fb6655a41e7b9c80491981eee2ff708c830c555..857f156e4985b4ed91ab304900b01eeaac8234ba 100644 (file)
@@ -167,12 +167,10 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
                        break;
                }
 
-#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
                if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) {
                        rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
                        break;
                }
-#endif
                if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
                        rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
                        break;
index 36a344a441c22327882d9d283a6603f9ddfe9c4a..59d48cf819ea8e1a51ac024b979996566cd3c2c3 100644 (file)
@@ -120,10 +120,8 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
                        dc_version = DCN_VERSION_1_01;
                if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
                        dc_version = DCN_VERSION_2_1;
-#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
                if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
                        dc_version = DCN_VERSION_2_1;
-#endif
                break;
 #endif
 
index 52fedddecada772a23c68bf7bb8427a8be96132d..ffcb059297d30faebc60d1ffde8c9d4f3d9a814e 100644 (file)
@@ -205,12 +205,10 @@ enum {
 #if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 #define ASICREV_IS_SIENNA_CICHLID_P(eChipRev)        ((eChipRev >= NV_SIENNA_CICHLID_P_A0))
 #endif
-#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
 #define GREEN_SARDINE_A0 0xA1
 #ifndef ASICREV_IS_GREEN_SARDINE
 #define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
 #endif
-#endif
 
 /*
  * ASIC chip ID