drm/i915/display: Disable FBC when PSR2 is enabled display 12 and newer

This is now a requirement for all display 12 and newer, not only for
tigerlake.

BSpec: 50422
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210625235600.765677-2-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 82effb64a3b9c4175c6180654de37e1ba42ab490..ddfc17e21668aebe0efe8fc57d5554ad434182e7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -912,11 +912,11 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
        }
 
        /*
-        * Tigerlake is not supporting FBC with PSR2.
+        * Display 12+ is not supporting FBC with PSR2.
         * Recommendation is to keep this combination disabled
         * Bspec: 50422 HSD: 14010260002
         */
-       if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) {
+       if (fbc->state_cache.psr2_active && DISPLAY_VER(dev_priv) >= 12) {
                fbc->no_fbc_reason = "not supported with PSR2";
                return false;
        }