PCI: Factor out pcie_retrain_link() function

BugLink: https://bugs.launchpad.net/bugs/1838576
commit 86fa6a344209d9414ea962b1f1ac6ade9dd7563a upstream.

Factor out pcie_retrain_link() to use for Pericom Retrain Link quirk.  No
functional change intended.

Signed-off-by: Stefan Mätje <stefan.maetje@esd.eu>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
CC: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Khalid Elmously <khalid.elmously@canonical.com>

diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index e96b15a7c54f210475afc695260797fee5007d3f..d4a5952e8e100263efe46de537b07301a7b445a4 100644 (file)
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -199,6 +199,29 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
        link->clkpm_capable = (blacklist) ? 0 : capable;
 }
 
+static bool pcie_retrain_link(struct pcie_link_state *link)
+{
+       struct pci_dev *parent = link->pdev;
+       unsigned long start_jiffies;
+       u16 reg16;
+
+       pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &reg16);
+       reg16 |= PCI_EXP_LNKCTL_RL;
+       pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
+
+       /* Wait for link training end. Break out after waiting for timeout */
+       start_jiffies = jiffies;
+       for (;;) {
+               pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &reg16);
+               if (!(reg16 & PCI_EXP_LNKSTA_LT))
+                       break;
+               if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
+                       break;
+               msleep(1);
+       }
+       return !(reg16 & PCI_EXP_LNKSTA_LT);
+}
+
 /*
  * pcie_aspm_configure_common_clock: check if the 2 ends of a link
  *   could use common clock. If they are, configure them to use the
@@ -208,7 +231,6 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
 {
        int same_clock = 1;
        u16 reg16, parent_reg, child_reg[8];
-       unsigned long start_jiffies;
        struct pci_dev *child, *parent = link->pdev;
        struct pci_bus *linkbus = parent->subordinate;
        /*
@@ -248,21 +270,7 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
                reg16 &= ~PCI_EXP_LNKCTL_CCC;
        pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
 
-       /* Retrain link */
-       reg16 |= PCI_EXP_LNKCTL_RL;
-       pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
-
-       /* Wait for link training end. Break out after waiting for timeout */
-       start_jiffies = jiffies;
-       for (;;) {
-               pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &reg16);
-               if (!(reg16 & PCI_EXP_LNKSTA_LT))
-                       break;
-               if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
-                       break;
-               msleep(1);
-       }
-       if (!(reg16 & PCI_EXP_LNKSTA_LT))
+       if (pcie_retrain_link(link))
                return;
 
        /* Training failed. Restore common clock configurations */