]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/commitdiff
mwifiex: update pcie8766 scratch register addresses
authorBing Zhao <bzhao@marvell.com>
Fri, 13 Apr 2012 02:00:35 +0000 (19:00 -0700)
committerJohn W. Linville <linville@tuxdriver.com>
Fri, 13 Apr 2012 18:06:59 +0000 (14:06 -0400)
The scratch register addresses have been changed for newer chips.
Since the old chip was never shipped and it will not be supported
any more, just update register addresses to support the new chips.

Cc: <stable@vger.kernel.org> # 3.2.y, 3.3.y
Signed-off-by: Bing Zhao <bzhao@marvell.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/mwifiex/pcie.h

index 445ff21772e2ec948948e6338525663b9b34f6eb..2f218f9a3fd3efea52e8038345a326bfb7341243 100644 (file)
 #define PCIE_HOST_INT_STATUS_MASK                      0xC3C
 #define PCIE_SCRATCH_2_REG                             0xC40
 #define PCIE_SCRATCH_3_REG                             0xC44
-#define PCIE_SCRATCH_4_REG                             0xCC0
-#define PCIE_SCRATCH_5_REG                             0xCC4
-#define PCIE_SCRATCH_6_REG                             0xCC8
-#define PCIE_SCRATCH_7_REG                             0xCCC
-#define PCIE_SCRATCH_8_REG                             0xCD0
-#define PCIE_SCRATCH_9_REG                             0xCD4
-#define PCIE_SCRATCH_10_REG                            0xCD8
-#define PCIE_SCRATCH_11_REG                            0xCDC
-#define PCIE_SCRATCH_12_REG                            0xCE0
+#define PCIE_SCRATCH_4_REG                             0xCD0
+#define PCIE_SCRATCH_5_REG                             0xCD4
+#define PCIE_SCRATCH_6_REG                             0xCD8
+#define PCIE_SCRATCH_7_REG                             0xCDC
+#define PCIE_SCRATCH_8_REG                             0xCE0
+#define PCIE_SCRATCH_9_REG                             0xCE4
+#define PCIE_SCRATCH_10_REG                            0xCE8
+#define PCIE_SCRATCH_11_REG                            0xCEC
+#define PCIE_SCRATCH_12_REG                            0xCF0
 
 #define CPU_INTR_DNLD_RDY                              BIT(0)
 #define CPU_INTR_DOOR_BELL                             BIT(1)