clocksource/drivers/imx-sysctr: Add internal clock divider handle

The system counter block guide states that the base clock is
internally divided by 3 before use, that means the clock input of
system counter defined in DT should be base clock which is normally
from OSC, and then internally divided by 3 before use.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

diff --git a/drivers/clocksource/timer-imx-sysctr.c b/drivers/clocksource/timer-imx-sysctr.c
index fd7d68066efb5414c0b7294069bdac142d691319..b7c80a368a1b1a544fb17c2f4212bf2875555977 100644 (file)
--- a/drivers/clocksource/timer-imx-sysctr.c
+++ b/drivers/clocksource/timer-imx-sysctr.c
@@ -20,6 +20,8 @@
 #define SYS_CTR_EN             0x1
 #define SYS_CTR_IRQ_MASK       0x2
 
+#define SYS_CTR_CLK_DIV                0x3
+
 static void __iomem *sys_ctr_base;
 static u32 cmpcr;
 
@@ -134,6 +136,9 @@ static int __init sysctr_timer_init(struct device_node *np)
        if (ret)
                return ret;
 
+       /* system counter clock is divided by 3 internally */
+       to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
+
        sys_ctr_base = timer_of_base(&to_sysctr);
        cmpcr = readl(sys_ctr_base + CMPCR);
        cmpcr &= ~SYS_CTR_EN;