};
# define PA_FMT "0x%08lx"
-# define REG_FMT "0x%lx"
+# define REG_FMT "0x" TARGET_FMT_plx
struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, DisplayState *ds,
const char *revision);
}
cpu_abort(cpu_single_env,
- "%s: Bad offset 0x%04lx\n", __FUNCTION__, offset);
+ "%s: Bad offset 0x" TARGET_FMT_plx "\n", __FUNCTION__, offset);
return 7;
}
break;
}
fail:
- cpu_abort(cpu_single_env, "%s: Bad offset 0x%04lx\n",
+ cpu_abort(cpu_single_env, "%s: Bad offset " TARGET_FMT_plx "\n",
__FUNCTION__, offset);
}
}
#define spitz_printf(format, ...) \
fprintf(stderr, "%s: " format, __FUNCTION__, ##__VA_ARGS__)
#undef REG_FMT
+#if TARGET_PHYS_ADDR_BITS == 32
+#define REG_FMT "0x%02x"
+#else
#define REG_FMT "0x%02lx"
+#endif
/* Spitz Flash */
#define FLASH_BASE 0x0c000000