@echo "missing libtool. please install and rerun configure."; exit 1
else
trace-dtrace.lo: trace-dtrace.dtrace
- $(call quiet-command,libtool --mode=compile --tag=CC dtrace -o $@ -G -s $<, " lt GEN trace-dtrace.o")
+ $(call quiet-command,$(LIBTOOL) --mode=compile --tag=CC dtrace -o $@ -G -s $<, " lt GEN trace-dtrace.o")
endif
simpletrace.o: simpletrace.c $(GENERATED_HEADERS)
cb, opaque);
if (ret) {
- /* Update stats even though technically transfer has not happened. */
- bs->rd_bytes += (unsigned) nb_sectors * BDRV_SECTOR_SIZE;
- bs->rd_ops ++;
+ /* Update stats even though technically transfer has not happened. */
+ bs->rd_bytes += (unsigned) nb_sectors * BDRV_SECTOR_SIZE;
+ bs->rd_ops++;
}
return ret;
int qemu_ftruncate64(int fd, int64_t length)
{
LARGE_INTEGER li;
+ DWORD dw;
LONG high;
HANDLE h;
BOOL res;
/* get current position, ftruncate do not change position */
li.HighPart = 0;
li.LowPart = SetFilePointer (h, 0, &li.HighPart, FILE_CURRENT);
- if (li.LowPart == 0xffffffffUL && GetLastError() != NO_ERROR)
+ if (li.LowPart == INVALID_SET_FILE_POINTER && GetLastError() != NO_ERROR) {
return -1;
+ }
high = length >> 32;
- if (!SetFilePointer(h, (DWORD) length, &high, FILE_BEGIN))
+ dw = SetFilePointer(h, (DWORD) length, &high, FILE_BEGIN);
+ if (dw == INVALID_SET_FILE_POINTER && GetLastError() != NO_ERROR) {
return -1;
+ }
res = SetEndOfFile(h);
/* back to old position */
ar="${AR-${cross_prefix}ar}"
objcopy="${OBJCOPY-${cross_prefix}objcopy}"
ld="${LD-${cross_prefix}ld}"
+libtool="${LIBTOOL-${cross_prefix}libtool}"
strip="${STRIP-${cross_prefix}strip}"
windres="${WINDRES-${cross_prefix}windres}"
pkg_config="${PKG_CONFIG-${cross_prefix}pkg-config}"
##########################################
# libtool probe
-if ! has libtool; then
+if ! has $libtool; then
libtool=
-else
- libtool=libtool
fi
##########################################
return len;
}
-static void console_send_event(CharDriverState *chr, int event)
-{
- TextConsole *s = chr->opaque;
- int i;
-
- if (event == CHR_EVENT_FOCUS) {
- for(i = 0; i < nb_consoles; i++) {
- if (consoles[i] == s) {
- console_select(i);
- break;
- }
- }
- }
-}
-
static void kbd_send_chars(void *opaque)
{
TextConsole *s = opaque;
int len;
uint8_t buf[16];
- len = qemu_chr_can_read(s->chr);
+ len = qemu_chr_be_can_write(s->chr);
if (len > s->out_fifo.count)
len = s->out_fifo.count;
if (len > 0) {
if (len > sizeof(buf))
len = sizeof(buf);
qemu_fifo_read(&s->out_fifo, buf, len);
- qemu_chr_read(s->chr, buf, len);
+ qemu_chr_be_write(s->chr, buf, len);
}
/* characters are pending: we send them a bit later (XXX:
horrible, should change char device API) */
s = chr->opaque;
chr->chr_write = console_puts;
- chr->chr_send_event = console_send_event;
s->out_fifo.buf = s->out_fifo_buf;
s->out_fifo.buf_size = sizeof(s->out_fifo_buf);
static QemuThread *tcg_cpu_thread;
static QemuCond *tcg_halt_cond;
-static int qemu_system_ready;
/* cpu creation */
static QemuCond qemu_cpu_cond;
/* system init */
-static QemuCond qemu_system_cond;
static QemuCond qemu_pause_cond;
static QemuCond qemu_work_cond;
}
qemu_cond_init(&qemu_cpu_cond);
- qemu_cond_init(&qemu_system_cond);
qemu_cond_init(&qemu_pause_cond);
qemu_cond_init(&qemu_work_cond);
qemu_cond_init(&qemu_io_proceeded_cond);
void qemu_main_loop_start(void)
{
- qemu_system_ready = 1;
- qemu_cond_broadcast(&qemu_system_cond);
+ resume_all_vcpus();
}
void run_on_cpu(CPUState *env, void (*func)(void *data), void *data)
env->created = 1;
qemu_cond_signal(&qemu_cpu_cond);
- /* and wait for machine initialization */
- while (!qemu_system_ready) {
- qemu_cond_wait(&qemu_system_cond, &qemu_global_mutex);
- }
-
while (1) {
if (cpu_can_run(env)) {
r = kvm_cpu_exec(env);
}
qemu_cond_signal(&qemu_cpu_cond);
- /* and wait for machine initialization */
- while (!qemu_system_ready) {
- qemu_cond_wait(&qemu_system_cond, &qemu_global_mutex);
+ /* wait for initial kick-off after machine start */
+ while (first_cpu->stopped) {
+ qemu_cond_wait(tcg_halt_cond, &qemu_global_mutex);
}
while (1) {
CPUState *env = _env;
qemu_cond_broadcast(env->halt_cond);
- if (!env->thread_kicked) {
+ if (kvm_enabled() && !env->thread_kicked) {
qemu_cpu_kick_thread(env);
env->thread_kicked = true;
}
env->thread = g_malloc0(sizeof(QemuThread));
env->halt_cond = g_malloc0(sizeof(QemuCond));
qemu_cond_init(env->halt_cond);
+ tcg_halt_cond = env->halt_cond;
qemu_thread_create(env->thread, qemu_tcg_cpu_thread_fn, env);
while (env->created == 0) {
qemu_cond_wait(&qemu_cpu_cond, &qemu_global_mutex);
}
tcg_cpu_thread = env->thread;
- tcg_halt_cond = env->halt_cond;
} else {
env->thread = tcg_cpu_thread;
env->halt_cond = tcg_halt_cond;
env->nr_cores = smp_cores;
env->nr_threads = smp_threads;
+ env->stopped = 1;
if (kvm_enabled()) {
qemu_kvm_start_vcpu(env);
} else {
}
}
#else
- qemu_chr_write(s->chr, buf, len);
+ qemu_chr_fe_write(s->chr, buf, len);
#endif
}
hextomem(mem_buf, p + 5, len);
len = len / 2;
mem_buf[len++] = 0;
- qemu_chr_read(s->mon_chr, mem_buf, len);
+ qemu_chr_be_write(s->mon_chr, mem_buf, len);
put_packet(s, "OK");
break;
}
#ifndef CONFIG_USER_ONLY
if (s->chr) {
- qemu_chr_close(s->chr);
+ qemu_chr_delete(s->chr);
}
#endif
}
sigaction(SIGINT, &act, NULL);
}
#endif
- chr = qemu_chr_open("gdb", device, NULL);
+ chr = qemu_chr_new("gdb", device, NULL);
if (!chr)
return -1;
monitor_init(mon_chr, 0);
} else {
if (s->chr)
- qemu_chr_close(s->chr);
+ qemu_chr_delete(s->chr);
mon_chr = s->mon_chr;
memset(s, 0, sizeof(GDBState));
}
#include "pci_host.h"
#include "pci_bridge.h"
#include "pci_internals.h"
-#include "rwhandler.h"
#include "apb_pci.h"
#include "sysemu.h"
#include "exec-memory.h"
typedef struct APBState {
SysBusDevice busdev;
PCIBus *bus;
- ReadWriteHandler pci_config_handler;
+ MemoryRegion apb_config;
+ MemoryRegion pci_config;
+ MemoryRegion pci_ioport;
uint32_t iommu[4];
uint32_t pci_control[16];
uint32_t pci_irq_map[8];
} APBState;
static void apb_config_writel (void *opaque, target_phys_addr_t addr,
- uint32_t val)
+ uint64_t val, unsigned size)
{
APBState *s = opaque;
}
}
-static uint32_t apb_config_readl (void *opaque,
- target_phys_addr_t addr)
+static uint64_t apb_config_readl (void *opaque,
+ target_phys_addr_t addr, unsigned size)
{
APBState *s = opaque;
uint32_t val;
return val;
}
-static CPUWriteMemoryFunc * const apb_config_write[] = {
- &apb_config_writel,
- &apb_config_writel,
- &apb_config_writel,
+static const MemoryRegionOps apb_config_ops = {
+ .read = apb_config_readl,
+ .write = apb_config_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUReadMemoryFunc * const apb_config_read[] = {
- &apb_config_readl,
- &apb_config_readl,
- &apb_config_readl,
-};
-
-static void apb_pci_config_write(ReadWriteHandler *h, pcibus_t addr,
- uint32_t val, int size)
+static void apb_pci_config_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
- APBState *s = container_of(h, APBState, pci_config_handler);
+ APBState *s = opaque;
val = qemu_bswap_len(val, size);
APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
pci_data_write(s->bus, addr, val, size);
}
-static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr,
- int size)
+static uint64_t apb_pci_config_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
uint32_t ret;
- APBState *s = container_of(h, APBState, pci_config_handler);
+ APBState *s = opaque;
ret = pci_data_read(s->bus, addr, size);
ret = qemu_bswap_len(ret, size);
return val;
}
-static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
- &pci_apb_iowriteb,
- &pci_apb_iowritew,
- &pci_apb_iowritel,
-};
-
-static CPUReadMemoryFunc * const pci_apb_ioread[] = {
- &pci_apb_ioreadb,
- &pci_apb_ioreadw,
- &pci_apb_ioreadl,
+static const MemoryRegionOps pci_ioport_ops = {
+ .old_mmio = {
+ .read = { pci_apb_ioreadb, pci_apb_ioreadw, pci_apb_ioreadl },
+ .write = { pci_apb_iowriteb, pci_apb_iowritew, pci_apb_iowritel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
/* The APB host has an IRQ line for each IRQ line of each slot. */
}
}
+static const MemoryRegionOps pci_config_ops = {
+ .read = apb_pci_config_read,
+ .write = apb_pci_config_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
static int pci_pbm_init_device(SysBusDevice *dev)
{
APBState *s;
- int pci_config, apb_config, pci_ioport;
unsigned int i;
s = FROM_SYSBUS(APBState, dev);
}
/* apb_config */
- apb_config = cpu_register_io_memory(apb_config_read,
- apb_config_write, s,
- DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->apb_config, &apb_config_ops, s, "apb-config",
+ 0x10000);
/* at region 0 */
- sysbus_init_mmio(dev, 0x10000ULL, apb_config);
+ sysbus_init_mmio_region(dev, &s->apb_config);
- /* PCI configuration space */
- s->pci_config_handler.read = apb_pci_config_read;
- s->pci_config_handler.write = apb_pci_config_write;
- pci_config = cpu_register_io_memory_simple(&s->pci_config_handler,
- DEVICE_NATIVE_ENDIAN);
- assert(pci_config >= 0);
+ memory_region_init_io(&s->pci_config, &pci_config_ops, s, "apb-pci-config",
+ 0x1000000);
/* at region 1 */
- sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
+ sysbus_init_mmio_region(dev, &s->pci_config);
/* pci_ioport */
- pci_ioport = cpu_register_io_memory(pci_apb_ioread,
- pci_apb_iowrite, s,
- DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->pci_ioport, &pci_ioport_ops, s,
+ "apb-pci-ioport", 0x10000);
/* at region 2 */
- sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
+ sysbus_init_mmio_region(dev, &s->pci_ioport);
return 0;
}
struct APICState {
SysBusDevice busdev;
+ MemoryRegion io_memory;
void *cpu_env;
uint32_t apicbase;
uint8_t id;
}
static void apic_bus_deliver(const uint32_t *deliver_bitmask,
- uint8_t delivery_mode,
- uint8_t vector_num, uint8_t polarity,
+ uint8_t delivery_mode, uint8_t vector_num,
uint8_t trigger_mode)
{
APICState *apic_iter;
apic_set_irq(apic_iter, vector_num, trigger_mode) );
}
-void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
- uint8_t delivery_mode, uint8_t vector_num,
- uint8_t polarity, uint8_t trigger_mode)
+void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
+ uint8_t vector_num, uint8_t trigger_mode)
{
uint32_t deliver_bitmask[MAX_APIC_WORDS];
trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
- polarity, trigger_mode);
+ trigger_mode);
apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
- apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
- trigger_mode);
+ apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
}
void cpu_set_apic_base(DeviceState *d, uint64_t val)
static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode,
uint8_t delivery_mode, uint8_t vector_num,
- uint8_t polarity, uint8_t trigger_mode)
+ uint8_t trigger_mode)
{
APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
uint32_t deliver_bitmask[MAX_APIC_WORDS];
return;
}
- apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
- trigger_mode);
+ apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
}
int apic_get_interrupt(DeviceState *d)
uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
/* XXX: Ignore redirection hint. */
- apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
+ apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
}
static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
s->icr[0] = val;
apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
- (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
+ (s->icr[0] >> 15) & 1);
break;
case 0x31:
s->icr[1] = val;
}
}
-static CPUReadMemoryFunc * const apic_mem_read[3] = {
- apic_mem_readb,
- apic_mem_readw,
- apic_mem_readl,
-};
-
-static CPUWriteMemoryFunc * const apic_mem_write[3] = {
- apic_mem_writeb,
- apic_mem_writew,
- apic_mem_writel,
+static const MemoryRegionOps apic_io_ops = {
+ .old_mmio = {
+ .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, },
+ .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int apic_init1(SysBusDevice *dev)
{
APICState *s = FROM_SYSBUS(APICState, dev);
- int apic_io_memory;
static int last_apic_idx;
if (last_apic_idx >= MAX_APICS) {
return -1;
}
- apic_io_memory = cpu_register_io_memory(apic_mem_read,
- apic_mem_write, NULL,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory);
+ memory_region_init_io(&s->io_memory, &apic_io_ops, s, "apic",
+ MSI_ADDR_SIZE);
+ sysbus_init_mmio_region(dev, &s->io_memory);
s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s);
s->idx = last_apic_idx++;
#include "qemu-common.h"
/* apic.c */
-void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
- uint8_t delivery_mode,
- uint8_t vector_num, uint8_t polarity,
- uint8_t trigger_mode);
+void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
+ uint8_t vector_num, uint8_t trigger_mode);
int apic_accept_pic_intr(DeviceState *s);
void apic_deliver_pic_intr(DeviceState *s, int level);
int apic_get_interrupt(DeviceState *s);
sysbus_mmio_map(s->priv, 0, base);
}
+static void mpcore_rirq_unmap(SysBusDevice *dev, target_phys_addr_t base)
+{
+ /* nothing to do */
+}
+
static int realview_mpcore_init(SysBusDevice *dev)
{
mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev);
}
}
qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);
- sysbus_init_mmio_cb(dev, 0x2000, mpcore_rirq_map);
+ sysbus_init_mmio_cb2(dev, mpcore_rirq_map, mpcore_rirq_unmap);
return 0;
}
int num_cpu;
#endif
- int iomemtype;
+ MemoryRegion iomem;
} gic_state;
/* TODO: Many places that call this routine could be optimized. */
gic_dist_writew(opaque, offset + 2, value >> 16);
}
-static CPUReadMemoryFunc * const gic_dist_readfn[] = {
- gic_dist_readb,
- gic_dist_readw,
- gic_dist_readl
-};
-
-static CPUWriteMemoryFunc * const gic_dist_writefn[] = {
- gic_dist_writeb,
- gic_dist_writew,
- gic_dist_writel
+static const MemoryRegionOps gic_dist_ops = {
+ .old_mmio = {
+ .read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, },
+ .write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
#ifndef NVIC
for (i = 0; i < NUM_CPU(s); i++) {
sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
}
- s->iomemtype = cpu_register_io_memory(gic_dist_readfn,
- gic_dist_writefn, s,
- DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000);
gic_reset(s);
register_savevm(NULL, "arm_gic", -1, 1, gic_save, gic_load, s);
}
typedef struct {
SysBusDevice busdev;
+ MemoryRegion iomem;
qemu_irq pl110_mux_ctrl;
uint32_t sys_id;
}
}
-static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
+static uint64_t arm_sysctl_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
}
static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
- uint32_t val)
+ uint64_t val, unsigned size)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
}
}
-static CPUReadMemoryFunc * const arm_sysctl_readfn[] = {
- arm_sysctl_read,
- arm_sysctl_read,
- arm_sysctl_read
-};
-
-static CPUWriteMemoryFunc * const arm_sysctl_writefn[] = {
- arm_sysctl_write,
- arm_sysctl_write,
- arm_sysctl_write
+static const MemoryRegionOps arm_sysctl_ops = {
+ .read = arm_sysctl_read,
+ .write = arm_sysctl_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void arm_sysctl_gpio_set(void *opaque, int line, int level)
static int arm_sysctl_init1(SysBusDevice *dev)
{
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
- int iomemtype;
- iomemtype = cpu_register_io_memory(arm_sysctl_readfn,
- arm_sysctl_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000);
+ sysbus_init_mmio_region(dev, &s->iomem);
qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1);
return 0;
typedef struct {
SysBusDevice busdev;
+ MemoryRegion iomem;
arm_timer_state *timer[2];
int level[2];
qemu_irq irq;
qemu_set_irq(s->irq, s->level[0] || s->level[1]);
}
-static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
+static uint64_t sp804_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
sp804_state *s = (sp804_state *)opaque;
}
static void sp804_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
sp804_state *s = (sp804_state *)opaque;
}
}
-static CPUReadMemoryFunc * const sp804_readfn[] = {
- sp804_read,
- sp804_read,
- sp804_read
+static const MemoryRegionOps sp804_ops = {
+ .read = sp804_read,
+ .write = sp804_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const sp804_writefn[] = {
- sp804_write,
- sp804_write,
- sp804_write
-};
-
-
static const VMStateDescription vmstate_sp804 = {
.name = "sp804",
.version_id = 1,
static int sp804_init(SysBusDevice *dev)
{
- int iomemtype;
sp804_state *s = FROM_SYSBUS(sp804_state, dev);
qemu_irq *qi;
s->timer[1] = arm_timer_init(1000000);
s->timer[0]->irq = qi[0];
s->timer[1]->irq = qi[1];
- iomemtype = cpu_register_io_memory(sp804_readfn,
- sp804_writefn, s, DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
+ sysbus_init_mmio_region(dev, &s->iomem);
vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
return 0;
}
typedef struct {
SysBusDevice busdev;
+ MemoryRegion iomem;
arm_timer_state *timer[3];
} icp_pit_state;
-static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
+static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
icp_pit_state *s = (icp_pit_state *)opaque;
int n;
}
static void icp_pit_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
icp_pit_state *s = (icp_pit_state *)opaque;
int n;
arm_timer_write(s->timer[n], offset & 0xff, value);
}
-
-static CPUReadMemoryFunc * const icp_pit_readfn[] = {
- icp_pit_read,
- icp_pit_read,
- icp_pit_read
-};
-
-static CPUWriteMemoryFunc * const icp_pit_writefn[] = {
- icp_pit_write,
- icp_pit_write,
- icp_pit_write
+static const MemoryRegionOps icp_pit_ops = {
+ .read = icp_pit_read,
+ .write = icp_pit_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int icp_pit_init(SysBusDevice *dev)
{
- int iomemtype;
icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);
/* Timer 0 runs at the system clock speed (40MHz). */
sysbus_init_irq(dev, &s->timer[1]->irq);
sysbus_init_irq(dev, &s->timer[2]->irq);
- iomemtype = cpu_register_io_memory(icp_pit_readfn,
- icp_pit_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &icp_pit_ops, s, "icp_pit", 0x1000);
+ sysbus_init_mmio_region(dev, &s->iomem);
/* This device has no state to save/restore. The component timers will
save themselves. */
return 0;
cpu_physical_memory_write(addr, (uint8_t *)&v, 4);
}
-static CPUReadMemoryFunc * const bitband_readfn[] = {
- bitband_readb,
- bitband_readw,
- bitband_readl
-};
-
-static CPUWriteMemoryFunc * const bitband_writefn[] = {
- bitband_writeb,
- bitband_writew,
- bitband_writel
+static const MemoryRegionOps bitband_ops = {
+ .old_mmio = {
+ .read = { bitband_readb, bitband_readw, bitband_readl, },
+ .write = { bitband_writeb, bitband_writew, bitband_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
typedef struct {
SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t base;
} BitBandState;
static int bitband_init(SysBusDevice *dev)
{
BitBandState *s = FROM_SYSBUS(BitBandState, dev);
- int iomemtype;
- iomemtype = cpu_register_io_memory(bitband_readfn, bitband_writefn,
- &s->base, DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, 0x02000000, iomemtype);
+ memory_region_init_io(&s->iomem, &bitband_ops, &s->base, "bitband",
+ 0x02000000);
+ sysbus_init_mmio_region(dev, &s->iomem);
return 0;
}
#include "sysbus.h"
#include "qemu-timer.h"
#include "arm-misc.h"
+#include "exec-memory.h"
/* 32 internal lines (16 used for system exceptions) plus 64 external
interrupt lines. */
nvic_state *s= FROM_SYSBUSGIC(nvic_state, dev);
gic_init(&s->gic);
- cpu_register_physical_memory(0xe000e000, 0x1000, s->gic.iomemtype);
+ memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->gic.iomem);
s->systick.timer = qemu_new_timer_ns(vm_clock, systick_timer_tick, s);
vmstate_register(&dev->qdev, -1, &vmstate_nvic, s);
return 0;
if (!baum->out_buf_used)
return;
- room = qemu_chr_can_read(chr);
+ room = qemu_chr_be_can_write(chr);
if (!room)
return;
if (room > baum->out_buf_used)
first = BUF_SIZE - baum->out_buf_ptr;
if (room > first) {
- qemu_chr_read(chr, baum->out_buf + baum->out_buf_ptr, first);
+ qemu_chr_be_write(chr, baum->out_buf + baum->out_buf_ptr, first);
baum->out_buf_ptr = 0;
baum->out_buf_used -= first;
room -= first;
}
- qemu_chr_read(chr, baum->out_buf + baum->out_buf_ptr, room);
+ qemu_chr_be_write(chr, baum->out_buf + baum->out_buf_ptr, room);
baum->out_buf_ptr += room;
baum->out_buf_used -= room;
}
while (len--)
if ((*cur++ = *buf++) == ESC)
*cur++ = ESC;
- room = qemu_chr_can_read(baum->chr);
+ room = qemu_chr_be_can_write(baum->chr);
len = cur - io_buf;
if (len <= room) {
/* Fits */
- qemu_chr_read(baum->chr, io_buf, len);
+ qemu_chr_be_write(baum->chr, io_buf, len);
} else {
int first;
uint8_t out;
/* Can't fit all, send what can be, and store the rest. */
- qemu_chr_read(baum->chr, io_buf, room);
+ qemu_chr_be_write(baum->chr, io_buf, room);
len -= room;
cur = io_buf + room;
if (len > BUF_SIZE - baum->out_buf_used) {
return orig_len;
}
-/* The other end sent us some event */
-static void baum_send_event(CharDriverState *chr, int event)
-{
- BaumDriverState *baum = chr->opaque;
- switch (event) {
- case CHR_EVENT_BREAK:
- break;
- case CHR_EVENT_OPENED:
- /* Reset state */
- baum->in_buf_used = 0;
- break;
- }
-}
-
/* Send the key code to the other end */
static void baum_send_key(BaumDriverState *baum, uint8_t type, uint8_t value) {
uint8_t packet[] = { type, value };
chr->opaque = baum;
chr->chr_write = baum_write;
- chr->chr_send_event = baum_send_event;
chr->chr_accept_input = baum_accept_input;
chr->chr_close = baum_close;
scr_msg_header.type = htonl(type);
scr_msg_header.reader_id = htonl(reader_id);
scr_msg_header.length = htonl(length);
- qemu_chr_write(s->cs, (uint8_t *)&scr_msg_header, sizeof(VSCMsgHeader));
- qemu_chr_write(s->cs, payload, length);
+ qemu_chr_fe_write(s->cs, (uint8_t *)&scr_msg_header, sizeof(VSCMsgHeader));
+ qemu_chr_fe_write(s->cs, payload, length);
}
static void ccid_card_vscard_send_apdu(PassthruState *s,
static void ccid_card_vscard_drop_connection(PassthruState *card)
{
- qemu_chr_close(card->cs);
+ qemu_chr_delete(card->cs);
card->vscard_in_pos = card->vscard_in_hdr = 0;
}
#include "console.h"
#include "vga_int.h"
#include "loader.h"
-#include "exec-memory.h"
/*
* TODO:
},
};
-static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
+static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci,
+ MemoryRegion *system_memory)
{
int i;
static int inited;
memory_region_init_io(&s->low_mem, &cirrus_vga_mem_ops, s,
"cirrus-low-memory", 0x20000);
memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
- memory_region_add_subregion_overlap(get_system_memory(),
+ memory_region_add_subregion_overlap(system_memory,
isa_mem_base + 0x000a0000,
&s->low_mem_container,
1);
*
***************************************/
-void isa_cirrus_vga_init(void)
+void isa_cirrus_vga_init(MemoryRegion *system_memory)
{
CirrusVGAState *s;
s = g_malloc0(sizeof(CirrusVGAState));
vga_common_init(&s->vga, VGA_RAM_SIZE);
- cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
+ cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0, system_memory);
s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
s->vga.screen_dump, s->vga.text_update,
&s->vga);
/* setup VGA */
vga_common_init(&s->vga, VGA_RAM_SIZE);
- cirrus_init_common(s, device_id, 1);
+ cirrus_init_common(s, device_id, 1, pci_address_space(dev));
s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
s->vga.screen_dump, s->vga.text_update,
&s->vga);
printf("debugcon: write addr=0x%04x val=0x%02x\n", addr, val);
#endif
- qemu_chr_write(s->chr, &ch, 1);
+ qemu_chr_fe_write(s->chr, &ch, 1);
}
void retu_key_event(void *retu, int state);
-/* tusb6010.c */
-typedef struct TUSBState TUSBState;
-TUSBState *tusb6010_init(qemu_irq intr);
-int tusb6010_sync_io(TUSBState *s);
-int tusb6010_async_io(TUSBState *s);
-void tusb6010_power(TUSBState *s, int on);
-
/* tc6393xb.c */
typedef struct TC6393xbState TC6393xbState;
#define TC6393XB_RAM 0x110000 /* amount of ram for Video and USB */
E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
uint32_t old_status = s->mac_reg[STATUS];
- if (nc->link_down)
+ if (nc->link_down) {
s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
- else
+ s->phy_reg[PHY_STATUS] &= ~MII_SR_LINK_STATUS;
+ } else {
s->mac_reg[STATUS] |= E1000_STATUS_LU;
+ s->phy_reg[PHY_STATUS] |= MII_SR_LINK_STATUS;
+ }
if (s->mac_reg[STATUS] != old_status)
set_ics(s, 0, E1000_ICR_LSC);
#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
+/* PHY Status Register */
+#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
+#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
+#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
+#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
+#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
+#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
+#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
+#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
+#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
+#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
+#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
+#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
+#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
+#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
+#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
+
/* Interrupt Cause Read */
#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
ssp.data_bits = data_bits;
ssp.stop_bits = stop_bits;
trace_escc_update_parameters(CHN_C(s), speed, parity, data_bits, stop_bits);
- qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
+ qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
static void escc_mem_write(void *opaque, target_phys_addr_t addr,
s->tx = val;
if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled
if (s->chr)
- qemu_chr_write(s->chr, &s->tx, 1);
+ qemu_chr_fe_write(s->chr, &s->tx, 1);
else if (s->type == kbd && !s->disabled) {
handle_kbd_command(s, val);
}
switch (addr)
{
case RW_DOUT:
- qemu_chr_write(s->chr, &ch, 1);
+ qemu_chr_fe_write(s->chr, &ch, 1);
s->regs[R_INTR] |= 3;
s->pending_tx = 1;
s->regs[addr] = value;
switch (addr) {
case DATA_OFFSET:
c = value & 0xFF;
- qemu_chr_write(uart->chr, &c, 1);
+ qemu_chr_fe_write(uart->chr, &c, 1);
return;
case STATUS_OFFSET:
#define PCI_MAPPING_ENTRY(regname) \
target_phys_addr_t regname ##_start; \
target_phys_addr_t regname ##_length; \
- int regname ##_handle
+ MemoryRegion regname ##_mem
typedef struct GT64120State {
SysBusDevice busdev;
target_phys_addr_t start = s->regs[GT_ISD] << 21;
target_phys_addr_t length = 0x1000;
- if (s->ISD_length)
- cpu_register_physical_memory(s->ISD_start, s->ISD_length,
- IO_MEM_UNASSIGNED);
+ if (s->ISD_length) {
+ memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
+ }
check_reserved_space(&start, &length);
length = 0x1000;
/* Map new address */
length, start, s->ISD_handle);
s->ISD_start = start;
s->ISD_length = length;
- cpu_register_physical_memory(s->ISD_start, s->ISD_length, s->ISD_handle);
+ memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
}
static void gt64120_pci_mapping(GT64120State *s)
/* Unmap old IO address */
if (s->PCI0IO_length)
{
- cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
+ memory_region_destroy(&s->PCI0IO_mem);
}
/* Map new IO address */
s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
isa_mem_base = s->PCI0IO_start;
- isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length);
+ if (s->PCI0IO_length) {
+ isa_mmio_setup(&s->PCI0IO_mem, s->PCI0IO_length);
+ memory_region_add_subregion(get_system_memory(), s->PCI0IO_start,
+ &s->PCI0IO_mem);
+ }
}
}
static void gt64120_writel (void *opaque, target_phys_addr_t addr,
- uint32_t val)
+ uint64_t val, unsigned size)
{
GT64120State *s = opaque;
uint32_t saddr;
}
}
-static uint32_t gt64120_readl (void *opaque,
- target_phys_addr_t addr)
+static uint64_t gt64120_readl (void *opaque,
+ target_phys_addr_t addr, unsigned size)
{
GT64120State *s = opaque;
uint32_t val;
return val;
}
-static CPUWriteMemoryFunc * const gt64120_write[] = {
- >64120_writel,
- >64120_writel,
- >64120_writel,
-};
-
-static CPUReadMemoryFunc * const gt64120_read[] = {
- >64120_readl,
- >64120_readl,
- >64120_readl,
+static const MemoryRegionOps isd_mem_ops = {
+ .read = gt64120_readl,
+ .write = gt64120_writel,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
get_system_memory(),
get_system_io(),
PCI_DEVFN(18, 0), 4);
- d->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, d,
- DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&d->ISD_mem, &isd_mem_ops, d, "isd-mem", 0x1000);
pci_create_simple(d->pci.bus, PCI_DEVFN(0, 0), "gt64120_pci");
return d->pci.bus;
uint64_t entry;
uint8_t dest;
uint8_t dest_mode;
- uint8_t polarity;
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
mask = 1 << i;
dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
delivery_mode =
(entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
- polarity = (entry >> IOAPIC_LVT_POLARITY_SHIFT) & 1;
if (trig_mode == IOAPIC_TRIGGER_EDGE) {
s->irr &= ~mask;
} else {
vector = entry & IOAPIC_VECTOR_MASK;
}
apic_deliver_irq(dest, dest_mode, delivery_mode,
- vector, polarity, trig_mode);
+ vector, trig_mode);
}
}
}
uint32_t mask = 1 << vector;
uint64_t entry = s->ioredtbl[vector];
+ if (entry & (1 << IOAPIC_LVT_POLARITY_SHIFT)) {
+ level = !level;
+ }
if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
IOAPIC_TRIGGER_LEVEL) {
/* level triggered */
#include "monitor.h"
#include "sysbus.h"
#include "isa.h"
+#include "exec-memory.h"
struct ISABus {
BusState qbus;
return strdup(path);
}
+MemoryRegion *isa_address_space(ISADevice *dev)
+{
+ return get_system_memory();
+}
+
device_init(isabus_register_devices)
void isa_init_ioport(ISADevice *dev, uint16_t ioport);
void isa_init_ioport_range(ISADevice *dev, uint16_t start, uint16_t length);
void isa_qdev_register(ISADeviceInfo *info);
+MemoryRegion *isa_address_space(ISADevice *dev);
ISADevice *isa_create(const char *name);
ISADevice *isa_try_create(const char *name);
ISADevice *isa_create_simple(const char *name);
memcpy(&incoming_posn, buf, sizeof(long));
/* pick off s->server_chr->msgfd and store it, posn should accompany msg */
- tmp_fd = qemu_chr_get_msgfd(s->server_chr);
+ tmp_fd = qemu_chr_fe_get_msgfd(s->server_chr);
IVSHMEM_DPRINTF("posn is %ld, fd is %d\n", incoming_posn, tmp_fd);
/* make sure we have enough space for this guest */
s->jtx = jtx;
if (s->chr) {
- qemu_chr_write(s->chr, &ch, 1);
+ qemu_chr_fe_write(s->chr, &ch, 1);
}
}
switch (addr) {
case R_RXTX:
if (s->chr) {
- qemu_chr_write(s->chr, &ch, 1);
+ qemu_chr_fe_write(s->chr, &ch, 1);
}
break;
case R_IER:
{
if (s->tx_enabled && (s->sr & MCF_UART_TxEMP) == 0) {
if (s->chr)
- qemu_chr_write(s->chr, (unsigned char *)&s->tb, 1);
+ qemu_chr_fe_write(s->chr, (unsigned char *)&s->tb, 1);
s->sr |= MCF_UART_TxEMP;
}
if (s->tx_enabled) {
#include "hw.h"
#include "pc.h"
+#include "microblaze_pic_cpu.h"
#define D(x)
cpu_reset_interrupt(env, type);
}
-qemu_irq *microblaze_pic_init_cpu(CPUState *env);
qemu_irq *microblaze_pic_init_cpu(CPUState *env)
{
return qemu_allocate_irqs(microblaze_pic_cpu_handler, env, 2);
--- /dev/null
+#ifndef MICROBLAZE_PIC_CPU_H
+#define MICROBLAZE_PIC_CPU_H
+
+#include "qemu-common.h"
+
+qemu_irq *microblaze_pic_init_cpu(CPUState *env);
+
+#endif /* MICROBLAZE_PIC_CPU_H */
switch (addr) {
case R_RXTX:
if (s->chr) {
- qemu_chr_write(s->chr, &ch, 1);
+ qemu_chr_fe_write(s->chr, &ch, 1);
}
trace_milkymist_uart_pulse_irq_tx();
qemu_irq_pulse(s->tx_irq);
#include "mc146818rtc.h"
#include "blockdev.h"
#include "sysbus.h"
+#include "exec-memory.h"
enum jazz_model_e
{
g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
break;
case JAZZ_PICA61:
- isa_vga_mm_init(0x40000000, 0x60000000, 0);
+ isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
break;
default:
break;
}
leds_text[8] = '\0';
- qemu_chr_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text);
- qemu_chr_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text);
+ qemu_chr_fe_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text);
+ qemu_chr_fe_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text);
}
/*
static void malta_fpga_led_init(CharDriverState *chr)
{
- qemu_chr_printf(chr, "\e[HMalta LEDBAR\r\n");
- qemu_chr_printf(chr, "+--------+\r\n");
- qemu_chr_printf(chr, "+ +\r\n");
- qemu_chr_printf(chr, "+--------+\r\n");
- qemu_chr_printf(chr, "\n");
- qemu_chr_printf(chr, "Malta ASCII\r\n");
- qemu_chr_printf(chr, "+--------+\r\n");
- qemu_chr_printf(chr, "+ +\r\n");
- qemu_chr_printf(chr, "+--------+\r\n");
+ qemu_chr_fe_printf(chr, "\e[HMalta LEDBAR\r\n");
+ qemu_chr_fe_printf(chr, "+--------+\r\n");
+ qemu_chr_fe_printf(chr, "+ +\r\n");
+ qemu_chr_fe_printf(chr, "+--------+\r\n");
+ qemu_chr_fe_printf(chr, "\n");
+ qemu_chr_fe_printf(chr, "Malta ASCII\r\n");
+ qemu_chr_fe_printf(chr, "+--------+\r\n");
+ qemu_chr_fe_printf(chr, "+ +\r\n");
+ qemu_chr_fe_printf(chr, "+--------+\r\n");
}
static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_irq, CharDriverState *uart_chr)
/* 0xa00 is less than a page, so will still get the right offsets. */
cpu_register_physical_memory(base + 0xa00, 0x100000 - 0xa00, malta);
- s->display = qemu_chr_open("fpga", "vc:320x200", malta_fpga_led_init);
+ s->display = qemu_chr_new("fpga", "vc:320x200", malta_fpga_led_init);
#ifdef TARGET_WORDS_BIGENDIAN
s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1, 1);
if (!serial_hds[i]) {
char label[32];
snprintf(label, sizeof(label), "serial%d", i);
- serial_hds[i] = qemu_chr_open(label, "null", NULL);
+ serial_hds[i] = qemu_chr_new(label, "null", NULL);
}
}
int iomemtype;
mpcore_timer_state timer[8];
uint32_t num_cpu;
+ MemoryRegion iomem;
+ MemoryRegion container;
} mpcore_priv_state;
/* Per-CPU Timers. */
/* Per-CPU private memory mapped IO. */
-static uint32_t mpcore_priv_read(void *opaque, target_phys_addr_t offset)
+static uint64_t mpcore_priv_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
int id;
}
static void mpcore_priv_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
int id;
hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
}
-static CPUReadMemoryFunc * const mpcore_priv_readfn[] = {
- mpcore_priv_read,
- mpcore_priv_read,
- mpcore_priv_read
+static const MemoryRegionOps mpcore_priv_ops = {
+ .read = mpcore_priv_read,
+ .write = mpcore_priv_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const mpcore_priv_writefn[] = {
- mpcore_priv_write,
- mpcore_priv_write,
- mpcore_priv_write
-};
-
-static void mpcore_priv_map(SysBusDevice *dev, target_phys_addr_t base)
+static void mpcore_priv_map_setup(mpcore_priv_state *s)
{
- mpcore_priv_state *s = FROM_SYSBUSGIC(mpcore_priv_state, dev);
- cpu_register_physical_memory(base, 0x1000, s->iomemtype);
- cpu_register_physical_memory(base + 0x1000, 0x1000, s->gic.iomemtype);
+ memory_region_init(&s->container, "mpcode-priv-container", 0x2000);
+ memory_region_init_io(&s->iomem, &mpcore_priv_ops, s, "mpcode-priv",
+ 0x1000);
+ memory_region_add_subregion(&s->container, 0, &s->iomem);
+ memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
}
static int mpcore_priv_init(SysBusDevice *dev)
int i;
gic_init(&s->gic, s->num_cpu);
- s->iomemtype = cpu_register_io_memory(mpcore_priv_readfn,
- mpcore_priv_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio_cb(dev, 0x2000, mpcore_priv_map);
+ mpcore_priv_map_setup(s);
+ sysbus_init_mmio_region(dev, &s->container);
for (i = 0; i < s->num_cpu * 2; i++) {
mpcore_timer_init(s, &s->timer[i], i);
}
/* We always send the packet of, so that we do not have to keep track
of previous state of the middle button. This can potentially confuse
some very old drivers for two button mice though. */
- qemu_chr_read(chr, bytes, 4);
+ qemu_chr_be_write(chr, bytes, 4);
}
static int msmouse_chr_write (struct CharDriverState *s, const uint8_t *buf, int len)
#include "bt.h"
#include "loader.h"
#include "blockdev.h"
+#include "tusb6010.h"
/* Nokia N8x0 support */
struct n800_s {
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef hw_omap_h
+#include "memory.h"
# define hw_omap_h "omap.h"
# define OMAP_EMIFS_BASE 0x00000000
struct omap_gpmc_s;
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
void omap_gpmc_reset(struct omap_gpmc_s *s);
-void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
+void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem,
void (*base_upd)(void *opaque, target_phys_addr_t new),
void (*unmap)(void *opaque), void *opaque);
if (ch == STI_TRACE_CONTROL_CHANNEL) {
/* Flush channel <i>value</i>. */
- qemu_chr_write(s->chr, (const uint8_t *) "\r", 1);
+ qemu_chr_fe_write(s->chr, (const uint8_t *) "\r", 1);
} else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
if (value == 0xc0 || value == 0xc3) {
/* Open channel <i>ch</i>. */
} else if (value == 0x00)
- qemu_chr_write(s->chr, (const uint8_t *) "\n", 1);
+ qemu_chr_fe_write(s->chr, (const uint8_t *) "\n", 1);
else
- qemu_chr_write(s->chr, &byte, 1);
+ qemu_chr_fe_write(s->chr, &byte, 1);
}
}
s->irq = irq;
omap_sti_reset(s);
- s->chr = chr ?: qemu_chr_open("null", "null", NULL);
+ s->chr = chr ?: qemu_chr_new("null", "null", NULL);
iomemtype = l4_register_io_memory(omap_sti_readfn,
omap_sti_writefn, s);
#include "hw.h"
#include "flash.h"
#include "omap.h"
+#include "memory.h"
+#include "exec-memory.h"
/* General-Purpose Memory Controller */
struct omap_gpmc_s {
qemu_irq irq;
+ MemoryRegion iomem;
uint8_t sysconfig;
uint16_t irqst;
uint32_t config[7];
target_phys_addr_t base;
size_t size;
- int iomemtype;
+ MemoryRegion *iomem;
+ MemoryRegion container;
void (*base_update)(void *opaque, target_phys_addr_t new);
void (*unmap)(void *opaque);
void *opaque;
* constant), the mask should cause wrapping of the address space, so
* that the same memory becomes accessible at every <i>size</i> bytes
* starting from <i>base</i>. */
- if (f->iomemtype)
- cpu_register_physical_memory(f->base, f->size, f->iomemtype);
+ if (f->iomem) {
+ memory_region_init(&f->container, "omap-gpmc-file", f->size);
+ memory_region_add_subregion(&f->container, 0, f->iomem);
+ memory_region_add_subregion(get_system_memory(), f->base,
+ &f->container);
+ }
if (f->base_update)
f->base_update(f->opaque, f->base);
if (f->size) {
if (f->unmap)
f->unmap(f->opaque);
- if (f->iomemtype)
- cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED);
+ if (f->iomem) {
+ memory_region_del_subregion(get_system_memory(), &f->container);
+ memory_region_del_subregion(&f->container, f->iomem);
+ memory_region_destroy(&f->container);
+ }
f->base = 0;
f->size = 0;
}
s->cs_file[i].config[6] & 0x1f, /* MASKADDR */
(s->cs_file[i].config[6] >> 8 & 0xf)); /* BASEADDR */
}
- omap_gpmc_cs_map(s->cs_file, 0, 0xf);
s->ecc_cs = 0;
s->ecc_ptr = 0;
s->ecc_cfg = 0x3fcff000;
ecc_reset(&s->ecc[i]);
}
-static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
int cs;
struct omap_gpmc_cs_file_s *f;
+ if (size != 4) {
+ return omap_badwidth_read32(opaque, addr);
+ }
+
switch (addr) {
case 0x000: /* GPMC_REVISION */
return 0x20;
}
static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
int cs;
struct omap_gpmc_cs_file_s *f;
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
switch (addr) {
case 0x000: /* GPMC_REVISION */
case 0x014: /* GPMC_SYSSTATUS */
case 0x010: /* GPMC_SYSCONFIG */
if ((value >> 3) == 0x3)
- fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
+ fprintf(stderr, "%s: bad SDRAM idle mode %"PRIi64"\n",
__FUNCTION__, value >> 3);
if (value & 2)
omap_gpmc_reset(s);
}
}
-static CPUReadMemoryFunc * const omap_gpmc_readfn[] = {
- omap_badwidth_read32, /* TODO */
- omap_badwidth_read32, /* TODO */
- omap_gpmc_read,
-};
-
-static CPUWriteMemoryFunc * const omap_gpmc_writefn[] = {
- omap_badwidth_write32, /* TODO */
- omap_badwidth_write32, /* TODO */
- omap_gpmc_write,
+static const MemoryRegionOps omap_gpmc_ops = {
+ .read = omap_gpmc_read,
+ .write = omap_gpmc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
{
- int iomemtype;
struct omap_gpmc_s *s = (struct omap_gpmc_s *)
g_malloc0(sizeof(struct omap_gpmc_s));
omap_gpmc_reset(s);
- iomemtype = cpu_register_io_memory(omap_gpmc_readfn,
- omap_gpmc_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_gpmc_ops, s, "omap-gpmc", 0x1000);
+ memory_region_add_subregion(get_system_memory(), base, &s->iomem);
return s;
}
-void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
+void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem,
void (*base_upd)(void *opaque, target_phys_addr_t new),
void (*unmap)(void *opaque), void *opaque)
{
}
f = &s->cs_file[cs];
- f->iomemtype = iomemtype;
+ f->iomem = iomem;
f->base_update = base_upd;
f->unmap = unmap;
f->opaque = opaque;
s->irq = irq;
#ifdef TARGET_WORDS_BIGENDIAN
s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
- chr ?: qemu_chr_open(label, "null", NULL), 1,
+ chr ?: qemu_chr_new(label, "null", NULL), 1,
1);
#else
s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
- chr ?: qemu_chr_open(label, "null", NULL), 1,
+ chr ?: qemu_chr_new(label, "null", NULL), 1,
0);
#endif
return s;
#ifdef TARGET_WORDS_BIGENDIAN
s->serial = serial_mm_init(s->base, 2, s->irq,
omap_clk_getrate(s->fclk) / 16,
- chr ?: qemu_chr_open("null", "null", NULL), 1,
+ chr ?: qemu_chr_new("null", "null", NULL), 1,
1);
#else
s->serial = serial_mm_init(s->base, 2, s->irq,
omap_clk_getrate(s->fclk) / 16,
- chr ?: qemu_chr_open("null", "null", NULL), 1,
+ chr ?: qemu_chr_new("null", "null", NULL), 1,
0);
#endif
}
#include "flash.h"
#include "irq.h"
#include "blockdev.h"
+#include "memory.h"
+#include "exec-memory.h"
/* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
#define PAGE_SHIFT 11
uint8_t *image;
uint8_t *otp;
uint8_t *current;
- ram_addr_t ram;
+ MemoryRegion ram;
+ MemoryRegion mapped_ram;
uint8_t *boot[2];
uint8_t *data[2][2];
- int iomemtype;
+ MemoryRegion iomem;
+ MemoryRegion container;
int cycle;
int otpmode;
ONEN_LOCK_UNLOCKED = 1 << 2,
};
+static void onenand_mem_setup(OneNANDState *s)
+{
+ /* XXX: We should use IO_MEM_ROMD but we broke it earlier...
+ * Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
+ * write boot commands. Also take note of the BWPS bit. */
+ memory_region_init(&s->container, "onenand", 0x10000 << s->shift);
+ memory_region_add_subregion(&s->container, 0, &s->iomem);
+ memory_region_init_alias(&s->mapped_ram, "onenand-mapped-ram",
+ &s->ram, 0x0200 << s->shift,
+ 0xbe00 << s->shift);
+ memory_region_add_subregion_overlap(&s->container,
+ 0x0200 << s->shift,
+ &s->mapped_ram,
+ 1);
+}
+
void onenand_base_update(void *opaque, target_phys_addr_t new)
{
OneNANDState *s = (OneNANDState *) opaque;
s->base = new;
- /* XXX: We should use IO_MEM_ROMD but we broke it earlier...
- * Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
- * write boot commands. Also take note of the BWPS bit. */
- cpu_register_physical_memory(s->base + (0x0000 << s->shift),
- 0x0200 << s->shift, s->iomemtype);
- cpu_register_physical_memory(s->base + (0x0200 << s->shift),
- 0xbe00 << s->shift,
- (s->ram +(0x0200 << s->shift)) | IO_MEM_RAM);
- if (s->iomemtype)
- cpu_register_physical_memory_offset(s->base + (0xc000 << s->shift),
- 0x4000 << s->shift, s->iomemtype, (0xc000 << s->shift));
+ memory_region_add_subregion(get_system_memory(), s->base, &s->container);
}
void onenand_base_unmap(void *opaque)
{
OneNANDState *s = (OneNANDState *) opaque;
- cpu_register_physical_memory(s->base,
- 0x10000 << s->shift, IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(), &s->container);
}
static void onenand_intr_update(OneNANDState *s)
onenand_intr_update(s);
}
-static uint32_t onenand_read(void *opaque, target_phys_addr_t addr)
+static uint64_t onenand_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
OneNANDState *s = (OneNANDState *) opaque;
int offset = addr >> s->shift;
}
static void onenand_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
OneNANDState *s = (OneNANDState *) opaque;
int offset = addr >> s->shift;
break;
default:
- fprintf(stderr, "%s: unknown OneNAND boot command %x\n",
+ fprintf(stderr, "%s: unknown OneNAND boot command %"PRIx64"\n",
__FUNCTION__, value);
}
break;
}
}
-static CPUReadMemoryFunc * const onenand_readfn[] = {
- onenand_read, /* TODO */
- onenand_read,
- onenand_read,
-};
-
-static CPUWriteMemoryFunc * const onenand_writefn[] = {
- onenand_write, /* TODO */
- onenand_write,
- onenand_write,
+static const MemoryRegionOps onenand_ops = {
+ .read = onenand_read,
+ .write = onenand_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
void *onenand_init(BlockDriverState *bdrv,
s->secs = size >> 9;
s->blockwp = g_malloc(s->blocks);
s->density_mask = (dev_id & 0x08) ? (1 << (6 + ((dev_id >> 4) & 7))) : 0;
- s->iomemtype = cpu_register_io_memory(onenand_readfn,
- onenand_writefn, s, DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->iomem, &onenand_ops, s, "onenand",
+ 0x10000 << s->shift);
s->bdrv = bdrv;
if (!s->bdrv) {
s->image = memset(g_malloc(size + (size >> 5)),
}
s->otp = memset(g_malloc((64 + 2) << PAGE_SHIFT),
0xff, (64 + 2) << PAGE_SHIFT);
- s->ram = qemu_ram_alloc(NULL, "onenand.ram", 0xc000 << s->shift);
- ram = qemu_get_ram_ptr(s->ram);
+ memory_region_init_ram(&s->ram, NULL, "onenand.ram", 0xc000 << s->shift);
+ ram = memory_region_get_ram_ptr(&s->ram);
s->boot[0] = ram + (0x0000 << s->shift);
s->boot[1] = ram + (0x8000 << s->shift);
s->data[0][0] = ram + ((0x0200 + (0 << (PAGE_SHIFT - 1))) << s->shift);
s->data[0][1] = ram + ((0x8010 + (0 << (PAGE_SHIFT - 6))) << s->shift);
s->data[1][0] = ram + ((0x0200 + (1 << (PAGE_SHIFT - 1))) << s->shift);
s->data[1][1] = ram + ((0x8010 + (1 << (PAGE_SHIFT - 6))) << s->shift);
+ onenand_mem_setup(s);
onenand_reset(s, 1);
if (val & PARA_CTR_STROBE) {
s->status &= ~PARA_STS_BUSY;
if ((s->control & PARA_CTR_STROBE) == 0)
- qemu_chr_write(s->chr, &s->dataw, 1);
+ qemu_chr_fe_write(s->chr, &s->dataw, 1);
} else {
if (s->control & PARA_CTR_INTEN) {
s->irq_pending = 1;
if (s->dataw == val)
return;
pdebug("wd%02x\n", val);
- qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
+ qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
s->dataw = val;
break;
case PARA_REG_STS:
} else {
dir = 0;
}
- qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
+ qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
parm &= ~PARA_CTR_DIR;
}
- qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
+ qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
s->control = val;
break;
case PARA_REG_EPP_ADDR:
pdebug("wa%02x s\n", val);
else {
struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
- if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
+ if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
s->epp_timeout = 1;
pdebug("wa%02x t\n", val);
}
pdebug("we%02x s\n", val);
else {
struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
- if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
+ if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
s->epp_timeout = 1;
pdebug("we%02x t\n", val);
}
pdebug("we%04x s\n", val);
return;
}
- err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
+ err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
if (err) {
s->epp_timeout = 1;
pdebug("we%04x t\n", val);
pdebug("we%08x s\n", val);
return;
}
- err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
+ err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
if (err) {
s->epp_timeout = 1;
pdebug("we%08x t\n", val);
addr &= 7;
switch(addr) {
case PARA_REG_DATA:
- qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
+ qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
if (s->last_read_offset != addr || s->datar != ret)
pdebug("rd%02x\n", ret);
s->datar = ret;
break;
case PARA_REG_STS:
- qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
+ qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
ret &= ~PARA_STS_TMOUT;
if (s->epp_timeout)
ret |= PARA_STS_TMOUT;
/* s->control has some bits fixed to 1. It is zero only when
it has not been yet written to. */
if (s->control == 0) {
- qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
+ qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
if (s->last_read_offset != addr)
pdebug("rc%02x\n", ret);
s->control = ret;
pdebug("ra%02x s\n", ret);
else {
struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
- if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
+ if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
s->epp_timeout = 1;
pdebug("ra%02x t\n", ret);
}
pdebug("re%02x s\n", ret);
else {
struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
- if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
+ if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
s->epp_timeout = 1;
pdebug("re%02x t\n", ret);
}
pdebug("re%04x s\n", eppdata);
return eppdata;
}
- err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
+ err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
ret = le16_to_cpu(eppdata);
if (err) {
pdebug("re%08x s\n", eppdata);
return eppdata;
}
- err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
+ err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
ret = le32_to_cpu(eppdata);
if (err) {
isa_init_irq(dev, &s->irq, isa->isairq);
qemu_register_reset(parallel_reset, s);
- if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
+ if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
s->hw_driver = 1;
s->status = dummy;
}
#include "blockdev.h"
#include "ui/qemu-spice.h"
#include "memory.h"
+#include "exec-memory.h"
/* output Bochs bios info messages */
//#define DEBUG_BIOS
const char *kernel_cmdline,
const char *initrd_filename,
ram_addr_t below_4g_mem_size,
- ram_addr_t above_4g_mem_size)
+ ram_addr_t above_4g_mem_size,
+ MemoryRegion *pci_memory,
+ MemoryRegion **ram_memory)
{
char *filename;
int ret, linux_boot, i;
ram = g_malloc(sizeof(*ram));
memory_region_init_ram(ram, NULL, "pc.ram",
below_4g_mem_size + above_4g_mem_size);
+ *ram_memory = ram;
ram_below_4g = g_malloc(sizeof(*ram_below_4g));
memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
0, below_4g_mem_size);
isa_bios = g_malloc(sizeof(*isa_bios));
memory_region_init_alias(isa_bios, "isa-bios", bios,
bios_size - isa_bios_size, isa_bios_size);
- memory_region_add_subregion_overlap(system_memory,
+ memory_region_add_subregion_overlap(pci_memory,
0x100000 - isa_bios_size,
isa_bios,
1);
option_rom_mr = g_malloc(sizeof(*option_rom_mr));
memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE);
- memory_region_add_subregion_overlap(system_memory,
+ memory_region_add_subregion_overlap(pci_memory,
PC_ROM_MIN_VGA,
option_rom_mr,
1);
/* map all the bios at the top of memory */
- memory_region_add_subregion(system_memory,
+ memory_region_add_subregion(pci_memory,
(uint32_t)(-bios_size),
bios);
if (pci_bus) {
pci_cirrus_vga_init(pci_bus);
} else {
- isa_cirrus_vga_init();
+ isa_cirrus_vga_init(get_system_memory());
}
} else if (vmsvga_enabled) {
if (pci_bus) {
const char *kernel_cmdline,
const char *initrd_filename,
ram_addr_t below_4g_mem_size,
- ram_addr_t above_4g_mem_size);
+ ram_addr_t above_4g_mem_size,
+ MemoryRegion *pci_memory,
+ MemoryRegion **ram_memory);
qemu_irq *pc_allocate_cpu_irq(void);
void pc_vga_init(PCIBus *pci_bus);
void pc_basic_device_init(qemu_irq *isa_irq,
qemu_irq *pic,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
- ram_addr_t ram_size);
-void i440fx_init_memory_mappings(PCII440FXState *d);
+ ram_addr_t ram_size,
+ target_phys_addr_t pci_hole_start,
+ target_phys_addr_t pci_hole_size,
+ target_phys_addr_t pci_hole64_start,
+ target_phys_addr_t pci_hole64_size,
+ MemoryRegion *pci_memory,
+ MemoryRegion *ram_memory);
/* piix4.c */
extern PCIDevice *piix4_dev;
int pci_vga_init(PCIBus *bus);
int isa_vga_mm_init(target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift);
+ target_phys_addr_t ctrl_base, int it_shift,
+ MemoryRegion *address_space);
/* cirrus_vga.c */
void pci_cirrus_vga_init(PCIBus *bus);
-void isa_cirrus_vga_init(void);
+void isa_cirrus_vga_init(MemoryRegion *address_space);
/* ne2000.c */
static inline bool isa_ne2000_init(int base, int irq, NICInfo *nd)
* THE SOFTWARE.
*/
+#include <glib.h>
+
#include "hw.h"
#include "pc.h"
#include "apic.h"
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
BusState *idebus[MAX_IDE_BUS];
ISADevice *rtc_state;
+ MemoryRegion *ram_memory;
+ MemoryRegion *pci_memory;
pc_cpus_init(cpu_model);
below_4g_mem_size = ram_size;
}
+ pci_memory = g_new(MemoryRegion, 1);
+ memory_region_init(pci_memory, "pci", INT64_MAX);
+
/* allocate ram and load rom/bios */
if (!xen_enabled()) {
pc_memory_init(system_memory,
kernel_filename, kernel_cmdline, initrd_filename,
- below_4g_mem_size, above_4g_mem_size);
+ below_4g_mem_size, above_4g_mem_size,
+ pci_memory, &ram_memory);
}
if (!xen_enabled()) {
if (pci_enabled) {
pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq,
- system_memory, system_io, ram_size);
+ system_memory, system_io, ram_size,
+ below_4g_mem_size,
+ 0x100000000ULL - below_4g_mem_size,
+ 0x100000000ULL + above_4g_mem_size,
+ (sizeof(target_phys_addr_t) == 4
+ ? 0
+ : ((uint64_t)1 << 62)),
+ pci_memory, ram_memory);
} else {
pci_bus = NULL;
i440fx_state = NULL;
smbus_eeprom_init(smbus, 8, NULL, 0);
}
- if (i440fx_state) {
- i440fx_init_memory_mappings(i440fx_state);
- }
-
if (pci_enabled) {
pc_pci_device_init(pci_bus);
}
return rc;
}
+
+MemoryRegion *pci_address_space(PCIDevice *dev)
+{
+ return dev->bus->address_space_mem;
+}
uint32_t address, uint32_t val, int len);
void pci_device_save(PCIDevice *s, QEMUFile *f);
int pci_device_load(PCIDevice *s, QEMUFile *f);
+MemoryRegion *pci_address_space(PCIDevice *dev);
typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
#include "hw.h"
#include "pci.h"
#include "pcie_host.h"
+#include "exec-memory.h"
/*
* PCI express mmcfig address
PCIE_MMCFG_DEVFN(mmcfg_addr));
}
-static void pcie_mmcfg_data_write(PCIBus *s,
- uint32_t mmcfg_addr, uint32_t val, int len)
+static void pcie_mmcfg_data_write(void *opaque, target_phys_addr_t mmcfg_addr,
+ uint64_t val, unsigned len)
{
+ PCIExpressHost *e = opaque;
+ PCIBus *s = e->pci.bus;
PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
uint32_t addr;
uint32_t limit;
pci_host_config_write_common(pci_dev, addr, limit, val, len);
}
-static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t mmcfg_addr, int len)
+static uint64_t pcie_mmcfg_data_read(void *opaque,
+ target_phys_addr_t mmcfg_addr,
+ unsigned len)
{
+ PCIExpressHost *e = opaque;
+ PCIBus *s = e->pci.bus;
PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
uint32_t addr;
uint32_t limit;
return pci_host_config_read_common(pci_dev, addr, limit, len);
}
-static void pcie_mmcfg_data_writeb(void *opaque,
- target_phys_addr_t addr, uint32_t value)
-{
- PCIExpressHost *e = opaque;
- pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 1);
-}
-
-static void pcie_mmcfg_data_writew(void *opaque,
- target_phys_addr_t addr, uint32_t value)
-{
- PCIExpressHost *e = opaque;
- pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 2);
-}
-
-static void pcie_mmcfg_data_writel(void *opaque,
- target_phys_addr_t addr, uint32_t value)
-{
- PCIExpressHost *e = opaque;
- pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 4);
-}
-
-static uint32_t pcie_mmcfg_data_readb(void *opaque, target_phys_addr_t addr)
-{
- PCIExpressHost *e = opaque;
- return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 1);
-}
-
-static uint32_t pcie_mmcfg_data_readw(void *opaque, target_phys_addr_t addr)
-{
- PCIExpressHost *e = opaque;
- return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 2);
-}
-
-static uint32_t pcie_mmcfg_data_readl(void *opaque, target_phys_addr_t addr)
-{
- PCIExpressHost *e = opaque;
- return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 4);
-}
-
-
-static CPUWriteMemoryFunc * const pcie_mmcfg_write[] =
-{
- pcie_mmcfg_data_writeb,
- pcie_mmcfg_data_writew,
- pcie_mmcfg_data_writel,
-};
-
-static CPUReadMemoryFunc * const pcie_mmcfg_read[] =
-{
- pcie_mmcfg_data_readb,
- pcie_mmcfg_data_readw,
- pcie_mmcfg_data_readl,
+static const MemoryRegionOps pcie_mmcfg_ops = {
+ .read = pcie_mmcfg_data_read,
+ .write = pcie_mmcfg_data_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
#define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL)
-int pcie_host_init(PCIExpressHost *e)
+int pcie_host_init(PCIExpressHost *e, uint32_t size)
{
+ assert(!(size & (size - 1))); /* power of 2 */
+ assert(size >= PCIE_MMCFG_SIZE_MIN);
+ assert(size <= PCIE_MMCFG_SIZE_MAX);
e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
- e->mmio_index =
- cpu_register_io_memory(pcie_mmcfg_read, pcie_mmcfg_write, e,
- DEVICE_NATIVE_ENDIAN);
- if (e->mmio_index < 0) {
- return -1;
- }
+ e->size = size;
+ memory_region_init_io(&e->mmio, &pcie_mmcfg_ops, e, "pcie-mmcfg", e->size);
return 0;
}
void pcie_host_mmcfg_unmap(PCIExpressHost *e)
{
if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) {
- cpu_register_physical_memory(e->base_addr, e->size, IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(), &e->mmio);
e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
}
}
-void pcie_host_mmcfg_map(PCIExpressHost *e,
- target_phys_addr_t addr, uint32_t size)
+void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr)
{
- assert(!(size & (size - 1))); /* power of 2 */
- assert(size >= PCIE_MMCFG_SIZE_MIN);
- assert(size <= PCIE_MMCFG_SIZE_MAX);
-
e->base_addr = addr;
- e->size = size;
- cpu_register_physical_memory(e->base_addr, e->size, e->mmio_index);
+ memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio);
}
void pcie_host_mmcfg_update(PCIExpressHost *e,
int enable,
- target_phys_addr_t addr, uint32_t size)
+ target_phys_addr_t addr)
{
pcie_host_mmcfg_unmap(e);
if (enable) {
- pcie_host_mmcfg_map(e, addr, size);
+ pcie_host_mmcfg_map(e, addr);
}
}
#define PCIE_HOST_H
#include "pci_host.h"
+#include "memory.h"
struct PCIExpressHost {
PCIHostState pci;
/* the size of MMCONFIG area. It's host bridge dependent */
target_phys_addr_t size;
- /* result of cpu_register_io_memory() to map MMCONFIG area */
- int mmio_index;
+ /* MMCONFIG mmio area */
+ MemoryRegion mmio;
};
-int pcie_host_init(PCIExpressHost *e);
+int pcie_host_init(PCIExpressHost *e, uint32_t size);
void pcie_host_mmcfg_unmap(PCIExpressHost *e);
-void pcie_host_mmcfg_map(PCIExpressHost *e,
- target_phys_addr_t addr, uint32_t size);
+void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr);
void pcie_host_mmcfg_update(PCIExpressHost *e,
int enable,
- target_phys_addr_t addr, uint32_t size);
+ target_phys_addr_t addr);
#endif /* PCIE_HOST_H */
pci_conf[PCI_MAX_LAT] = 0xff;
/* Handler for memory-mapped I/O */
- memory_region_init_io(&d->state.mmio, &pcnet_mmio_ops, d, "pcnet-mmio",
+ memory_region_init_io(&d->state.mmio, &pcnet_mmio_ops, s, "pcnet-mmio",
PCNET_PNPMMIO_SIZE);
- memory_region_init_io(&d->io_bar, &pcnet_io_ops, d, "pcnet-io",
+ memory_region_init_io(&d->io_bar, &pcnet_io_ops, s, "pcnet-io",
PCNET_IOPORT_SIZE);
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar);
#include "blockdev.h"
#include "pc.h"
+#include "microblaze_pic_cpu.h"
#include "xilinx_axidma.h"
#define LMB_BRAM_SIZE (128 * 1024)
#include "elf.h"
#include "blockdev.h"
+#include "microblaze_pic_cpu.h"
+
#define LMB_BRAM_SIZE (128 * 1024)
#define FLASH_SIZE (16 * 1024 * 1024)
int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
} PIIX3State;
+typedef struct PAMMemoryRegion {
+ MemoryRegion mem;
+ bool initialized;
+} PAMMemoryRegion;
+
struct PCII440FXState {
PCIDevice dev;
- target_phys_addr_t isa_page_descs[384 / 4];
+ MemoryRegion *system_memory;
+ MemoryRegion *pci_address_space;
+ MemoryRegion *ram_memory;
+ MemoryRegion pci_hole;
+ MemoryRegion pci_hole_64bit;
+ PAMMemoryRegion pam_regions[13];
+ MemoryRegion smram_region;
uint8_t smm_enabled;
+ bool smram_enabled;
PIIX3State *piix3;
};
return (pci_intx + slot_addend) & 3;
}
-static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
+static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r,
+ PAMMemoryRegion *mem)
{
- uint32_t addr;
+ if (mem->initialized) {
+ memory_region_del_subregion(d->system_memory, &mem->mem);
+ memory_region_destroy(&mem->mem);
+ }
// printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
switch(r) {
case 3:
/* RAM */
- cpu_register_physical_memory(start, end - start,
- start);
+ memory_region_init_alias(&mem->mem, "pam-ram", d->ram_memory,
+ start, end - start);
break;
case 1:
/* ROM (XXX: not quite correct) */
- cpu_register_physical_memory(start, end - start,
- start | IO_MEM_ROM);
+ memory_region_init_alias(&mem->mem, "pam-rom", d->ram_memory,
+ start, end - start);
+ memory_region_set_readonly(&mem->mem, true);
break;
case 2:
case 0:
/* XXX: should distinguish read/write cases */
- for(addr = start; addr < end; addr += 4096) {
- cpu_register_physical_memory(addr, 4096,
- d->isa_page_descs[(addr - 0xa0000) >> 12]);
- }
+ memory_region_init_alias(&mem->mem, "pam-pci", d->pci_address_space,
+ start, end - start);
break;
}
+ memory_region_add_subregion_overlap(d->system_memory,
+ start, &mem->mem, 1);
+ mem->initialized = true;
}
static void i440fx_update_memory_mappings(PCII440FXState *d)
{
int i, r;
- uint32_t smram, addr;
+ uint32_t smram;
- update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
+ update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3,
+ &d->pam_regions[0]);
for(i = 0; i < 12; i++) {
r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
- update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
+ update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r,
+ &d->pam_regions[i+1]);
}
smram = d->dev.config[I440FX_SMRAM];
if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
- cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
+ if (!d->smram_enabled) {
+ memory_region_del_subregion(d->system_memory, &d->smram_region);
+ d->smram_enabled = true;
+ }
} else {
- for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
- cpu_register_physical_memory(addr, 4096,
- d->isa_page_descs[(addr - 0xa0000) >> 12]);
+ if (d->smram_enabled) {
+ memory_region_add_subregion_overlap(d->system_memory, 0xa0000,
+ &d->smram_region, 1);
+ d->smram_enabled = false;
}
}
}
}
-/* XXX: suppress when better memory API. We make the assumption that
- no device (in particular the VGA) changes the memory mappings in
- the 0xa0000-0x100000 range */
-void i440fx_init_memory_mappings(PCII440FXState *d)
-{
- int i;
- for(i = 0; i < 96; i++) {
- d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
- }
-}
-
static void i440fx_write_config(PCIDevice *dev,
uint32_t address, uint32_t val, int len)
{
qemu_irq *pic,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
- ram_addr_t ram_size)
+ ram_addr_t ram_size,
+ target_phys_addr_t pci_hole_start,
+ target_phys_addr_t pci_hole_size,
+ target_phys_addr_t pci_hole64_start,
+ target_phys_addr_t pci_hole64_size,
+ MemoryRegion *pci_address_space,
+ MemoryRegion *ram_memory)
{
DeviceState *dev;
PCIBus *b;
PCIDevice *d;
I440FXState *s;
PIIX3State *piix3;
+ PCII440FXState *f;
dev = qdev_create(NULL, "i440FX-pcihost");
s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
s->address_space = address_space_mem;
- b = pci_bus_new(&s->busdev.qdev, NULL, s->address_space,
+ b = pci_bus_new(&s->busdev.qdev, NULL, pci_address_space,
address_space_io, 0);
s->bus = b;
qdev_init_nofail(dev);
d = pci_create_simple(b, 0, device_name);
*pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
+ f = *pi440fx_state;
+ f->system_memory = address_space_mem;
+ f->pci_address_space = pci_address_space;
+ f->ram_memory = ram_memory;
+ memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
+ pci_hole_start, pci_hole_size);
+ memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
+ memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
+ f->pci_address_space,
+ pci_hole64_start, pci_hole64_size);
+ if (pci_hole64_size) {
+ memory_region_add_subregion(f->system_memory, pci_hole64_start,
+ &f->pci_hole_64bit);
+ }
+ memory_region_init_alias(&f->smram_region, "smram-region",
+ f->pci_address_space, 0xa0000, 0x20000);
+ f->smram_enabled = true;
/* Xen supports additional interrupt routes from the PCI devices to
* the IOAPIC: the four pins of each PCI device on the bus are also
ram_size = 255;
(*pi440fx_state)->dev.config[0x57]=ram_size;
+ i440fx_update_memory_mappings(f);
+
return b;
}
qemu_irq *pic,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
- ram_addr_t ram_size)
+ ram_addr_t ram_size,
+ target_phys_addr_t pci_hole_start,
+ target_phys_addr_t pci_hole_size,
+ target_phys_addr_t pci_hole64_start,
+ target_phys_addr_t pci_hole64_size,
+ MemoryRegion *pci_memory, MemoryRegion *ram_memory)
+
{
PCIBus *b;
b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic,
- address_space_mem, address_space_io, ram_size);
+ address_space_mem, address_space_io, ram_size,
+ pci_hole_start, pci_hole_size,
+ pci_hole64_size, pci_hole64_size,
+ pci_memory, ram_memory);
return b;
}
/* ??? Check if transmitter is enabled. */
ch = value;
if (s->chr)
- qemu_chr_write(s->chr, &ch, 1);
+ qemu_chr_fe_write(s->chr, &ch, 1);
s->int_level |= PL011_INT_TX;
pl011_update(s);
break;
ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
uint32_t flags);
-CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
+CPUState *ppc405cr_init (MemoryRegion ram_memories[4],
+ target_phys_addr_t ram_bases[4],
target_phys_addr_t ram_sizes[4],
uint32_t sysclk, qemu_irq **picp,
int do_init);
-CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
+CPUState *ppc405ep_init (MemoryRegion ram_memories[2],
+ target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
int do_init);
/* IBM STBxxx microcontrollers */
-CPUState *ppc_stb025_init (target_phys_addr_t ram_bases[2],
+CPUState *ppc_stb025_init (MemoryRegion ram_memories[2],
+ target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
ram_addr_t *offsetp);
CPUPPCState *env;
qemu_irq *pic;
ram_addr_t sram_offset, bios_offset, bdloc;
+ MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2];
target_ulong sram_size;
long bios_size;
DriveInfo *dinfo;
/* XXX: fix this */
- ram_bases[0] = qemu_ram_alloc(NULL, "ef405ep.ram", 0x08000000);
+ memory_region_init_ram(&ram_memories[0], NULL, "ef405ep.ram", 0x08000000);
+ ram_bases[0] = 0;
ram_sizes[0] = 0x08000000;
+ memory_region_init(&ram_memories[1], "ef405ep.ram1", 0);
ram_bases[1] = 0x00000000;
ram_sizes[1] = 0x00000000;
ram_size = 128 * 1024 * 1024;
#ifdef DEBUG_BOARD_INIT
printf("%s: register cpu\n", __func__);
#endif
- env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
+ env = ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic,
kernel_filename == NULL ? 0 : 1);
/* allocate SRAM */
sram_size = 512 * 1024;
char *filename;
qemu_irq *pic;
ram_addr_t bios_offset;
+ MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2];
long bios_size;
target_ulong kernel_base, initrd_base;
DriveInfo *dinfo;
/* RAM is soldered to the board so the size cannot be changed */
- ram_bases[0] = qemu_ram_alloc(NULL, "taihu_405ep.ram-0", 0x04000000);
+ memory_region_init_ram(&ram_memories[0], NULL,
+ "taihu_405ep.ram-0", 0x04000000);
+ ram_bases[0] = 0;
ram_sizes[0] = 0x04000000;
- ram_bases[1] = qemu_ram_alloc(NULL, "taihu_405ep.ram-1", 0x04000000);
+ memory_region_init_ram(&ram_memories[1], NULL,
+ "taihu_405ep.ram-1", 0x04000000);
+ ram_bases[1] = 0x04000000;
ram_sizes[1] = 0x04000000;
ram_size = 0x08000000;
#ifdef DEBUG_BOARD_INIT
printf("%s: register cpu\n", __func__);
#endif
- ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
+ ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic,
kernel_filename == NULL ? 0 : 1);
/* allocate and load BIOS */
#ifdef DEBUG_BOARD_INIT
#include "qemu-timer.h"
#include "sysemu.h"
#include "qemu-log.h"
+#include "exec-memory.h"
#define DEBUG_OPBA
#define DEBUG_SDRAM
/* OPB arbitrer */
typedef struct ppc4xx_opba_t ppc4xx_opba_t;
struct ppc4xx_opba_t {
+ MemoryRegion io;
uint8_t cr;
uint8_t pr;
};
opba_writeb(opaque, addr + 1, value >> 16);
}
-static CPUReadMemoryFunc * const opba_read[] = {
- &opba_readb,
- &opba_readw,
- &opba_readl,
-};
-
-static CPUWriteMemoryFunc * const opba_write[] = {
- &opba_writeb,
- &opba_writew,
- &opba_writel,
+static const MemoryRegionOps opba_ops = {
+ .old_mmio = {
+ .read = { opba_readb, opba_readw, opba_readl, },
+ .write = { opba_writeb, opba_writew, opba_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void ppc4xx_opba_reset (void *opaque)
static void ppc4xx_opba_init(target_phys_addr_t base)
{
ppc4xx_opba_t *opba;
- int io;
opba = g_malloc0(sizeof(ppc4xx_opba_t));
#ifdef DEBUG_OPBA
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(opba_read, opba_write, opba,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x002, io);
+ memory_region_init_io(&opba->io, &opba_ops, opba, "opba", 0x002);
+ memory_region_add_subregion(get_system_memory(), base, &opba->io);
qemu_register_reset(ppc4xx_opba_reset, opba);
}
/* GPIO */
typedef struct ppc405_gpio_t ppc405_gpio_t;
struct ppc405_gpio_t {
+ MemoryRegion io;
uint32_t or;
uint32_t tcr;
uint32_t osrh;
#endif
}
-static CPUReadMemoryFunc * const ppc405_gpio_read[] = {
- &ppc405_gpio_readb,
- &ppc405_gpio_readw,
- &ppc405_gpio_readl,
-};
-
-static CPUWriteMemoryFunc * const ppc405_gpio_write[] = {
- &ppc405_gpio_writeb,
- &ppc405_gpio_writew,
- &ppc405_gpio_writel,
+static const MemoryRegionOps ppc405_gpio_ops = {
+ .old_mmio = {
+ .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },
+ .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void ppc405_gpio_reset (void *opaque)
static void ppc405_gpio_init(target_phys_addr_t base)
{
ppc405_gpio_t *gpio;
- int io;
gpio = g_malloc0(sizeof(ppc405_gpio_t));
#ifdef DEBUG_GPIO
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x038, io);
+ memory_region_init_io(&gpio->io, &ppc405_gpio_ops, gpio, "pgio", 0x038);
+ memory_region_add_subregion(get_system_memory(), base, &gpio->io);
qemu_register_reset(&ppc405_gpio_reset, gpio);
}
typedef struct ppc405_ocm_t ppc405_ocm_t;
struct ppc405_ocm_t {
- target_ulong offset;
+ MemoryRegion ram;
+ MemoryRegion isarc_ram;
+ MemoryRegion dsarc_ram;
uint32_t isarc;
uint32_t isacntl;
uint32_t dsarc;
if (ocm->isacntl & 0x80000000) {
/* Unmap previously assigned memory region */
printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
- cpu_register_physical_memory(ocm->isarc, 0x04000000,
- IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
}
if (isacntl & 0x80000000) {
/* Map new instruction memory region */
#ifdef DEBUG_OCM
printf("OCM map ISA %08" PRIx32 "\n", isarc);
#endif
- cpu_register_physical_memory(isarc, 0x04000000,
- ocm->offset | IO_MEM_RAM);
+ memory_region_add_subregion(get_system_memory(), isarc,
+ &ocm->isarc_ram);
}
}
if (ocm->dsarc != dsarc ||
#ifdef DEBUG_OCM
printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
#endif
- cpu_register_physical_memory(ocm->dsarc, 0x04000000,
- IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(),
+ &ocm->dsarc_ram);
}
}
if (dsacntl & 0x80000000) {
#ifdef DEBUG_OCM
printf("OCM map DSA %08" PRIx32 "\n", dsarc);
#endif
- cpu_register_physical_memory(dsarc, 0x04000000,
- ocm->offset | IO_MEM_RAM);
+ memory_region_add_subregion(get_system_memory(), dsarc,
+ &ocm->dsarc_ram);
}
}
}
ppc405_ocm_t *ocm;
ocm = g_malloc0(sizeof(ppc405_ocm_t));
- ocm->offset = qemu_ram_alloc(NULL, "ppc405.ocm", 4096);
+ /* XXX: Size is 4096 or 0x04000000 */
+ memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096);
+ memory_region_init_alias(&ocm->dsarc_ram, "ppc405.dsarc", &ocm->isarc_ram,
+ 0, 4096);
qemu_register_reset(&ocm_reset, ocm);
ppc_dcr_register(env, OCM0_ISARC,
ocm, &dcr_read_ocm, &dcr_write_ocm);
typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
struct ppc4xx_i2c_t {
qemu_irq irq;
+ MemoryRegion iomem;
uint8_t mdata;
uint8_t lmadr;
uint8_t hmadr;
ppc4xx_i2c_writeb(opaque, addr + 3, value);
}
-static CPUReadMemoryFunc * const i2c_read[] = {
- &ppc4xx_i2c_readb,
- &ppc4xx_i2c_readw,
- &ppc4xx_i2c_readl,
-};
-
-static CPUWriteMemoryFunc * const i2c_write[] = {
- &ppc4xx_i2c_writeb,
- &ppc4xx_i2c_writew,
- &ppc4xx_i2c_writel,
+static const MemoryRegionOps i2c_ops = {
+ .old_mmio = {
+ .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
+ .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void ppc4xx_i2c_reset (void *opaque)
static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
{
ppc4xx_i2c_t *i2c;
- int io;
i2c = g_malloc0(sizeof(ppc4xx_i2c_t));
i2c->irq = irq;
#ifdef DEBUG_I2C
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(i2c_read, i2c_write, i2c,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x011, io);
+ memory_region_init_io(&i2c->iomem, &i2c_ops, i2c, "i2c", 0x011);
+ memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
qemu_register_reset(ppc4xx_i2c_reset, i2c);
}
/* General purpose timers */
typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
struct ppc4xx_gpt_t {
+ MemoryRegion iomem;
int64_t tb_offset;
uint32_t tb_freq;
struct QEMUTimer *timer;
}
}
-static CPUReadMemoryFunc * const gpt_read[] = {
- &ppc4xx_gpt_readb,
- &ppc4xx_gpt_readw,
- &ppc4xx_gpt_readl,
-};
-
-static CPUWriteMemoryFunc * const gpt_write[] = {
- &ppc4xx_gpt_writeb,
- &ppc4xx_gpt_writew,
- &ppc4xx_gpt_writel,
+static const MemoryRegionOps gpt_ops = {
+ .old_mmio = {
+ .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },
+ .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void ppc4xx_gpt_cb (void *opaque)
{
ppc4xx_gpt_t *gpt;
int i;
- int io;
gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
for (i = 0; i < 5; i++) {
#ifdef DEBUG_GPT
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(gpt_read, gpt_write, gpt, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x0d4, io);
+ memory_region_init_io(&gpt->iomem, &gpt_ops, gpt, "gpt", 0x0d4);
+ memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
qemu_register_reset(ppc4xx_gpt_reset, gpt);
}
qemu_register_reset(ppc405cr_cpc_reset, cpc);
}
-CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
+CPUState *ppc405cr_init (MemoryRegion ram_memories[4],
+ target_phys_addr_t ram_bases[4],
target_phys_addr_t ram_sizes[4],
uint32_t sysclk, qemu_irq **picp,
int do_init)
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
*picp = pic;
/* SDRAM controller */
- ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
+ ppc4xx_sdram_init(env, pic[14], 1, ram_memories,
+ ram_bases, ram_sizes, do_init);
/* External bus controller */
ppc405_ebc_init(env);
/* DMA controller */
#endif
}
-CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
+CPUState *ppc405ep_init (MemoryRegion ram_memories[2],
+ target_phys_addr_t ram_bases[2],
target_phys_addr_t ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
int do_init)
*picp = pic;
/* SDRAM controller */
/* XXX 405EP has no ECC interrupt */
- ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init);
+ ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
+ ram_bases, ram_sizes, do_init);
/* External bus controller */
ppc405_ebc_init(env);
/* DMA controller */
const unsigned int pci_irq_nrs[4], int do_init,
const char *cpu_model)
{
+ MemoryRegion *ram_memories
+ = g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories));
target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];
target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];
CPUState *env;
memset(ram_bases, 0, sizeof(ram_bases));
memset(ram_sizes, 0, sizeof(ram_sizes));
*ram_size = ppc4xx_sdram_adjust(*ram_size, PPC440EP_SDRAM_NR_BANKS,
+ ram_memories,
ram_bases, ram_sizes,
ppc440ep_sdram_bank_sizes);
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
- ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_bases,
- ram_sizes, do_init);
+ ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories,
+ ram_bases, ram_sizes, do_init);
/* PCI */
pci_irqs = g_malloc(sizeof(qemu_irq) * 4);
uint32_t dcr_base, int has_ssr, int has_vr);
ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
+ MemoryRegion ram_memories[],
target_phys_addr_t ram_bases[],
target_phys_addr_t ram_sizes[],
const unsigned int sdram_bank_sizes[]);
void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
+ MemoryRegion ram_memories[],
target_phys_addr_t *ram_bases,
target_phys_addr_t *ram_sizes,
int do_init);
#include "ppc.h"
#include "ppc4xx.h"
#include "qemu-log.h"
+#include "exec-memory.h"
//#define DEBUG_MMIO
//#define DEBUG_UNASSIGNED
struct ppc4xx_sdram_t {
uint32_t addr;
int nbanks;
+ MemoryRegion containers[4]; /* used for clipping */
+ MemoryRegion *ram_memories;
target_phys_addr_t ram_bases[4];
target_phys_addr_t ram_sizes[4];
uint32_t besr0;
return size;
}
-static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
+static void sdram_set_bcr(ppc4xx_sdram_t *sdram,
+ uint32_t *bcrp, uint32_t bcr, int enabled)
{
+ unsigned n = bcrp - sdram->bcr;
+
if (*bcrp & 0x00000001) {
/* Unmap RAM */
#ifdef DEBUG_SDRAM
printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(*bcrp), sdram_size(*bcrp));
#endif
- cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
- IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(),
+ &sdram->containers[n]);
+ memory_region_del_subregion(&sdram->containers[n],
+ &sdram->ram_memories[n]);
+ memory_region_destroy(&sdram->containers[n]);
}
*bcrp = bcr & 0xFFDEE001;
if (enabled && (bcr & 0x00000001)) {
printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(bcr), sdram_size(bcr));
#endif
- cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
- sdram_base(bcr) | IO_MEM_RAM);
+ memory_region_init(&sdram->containers[n], "sdram-containers",
+ sdram_size(bcr));
+ memory_region_add_subregion(&sdram->containers[n], 0,
+ &sdram->ram_memories[n]);
+ memory_region_add_subregion(get_system_memory(),
+ sdram_base(bcr),
+ &sdram->containers[n]);
}
}
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->ram_sizes[i] != 0) {
- sdram_set_bcr(&sdram->bcr[i],
+ sdram_set_bcr(sdram,
+ &sdram->bcr[i],
sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
1);
} else {
- sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0);
+ sdram_set_bcr(sdram, &sdram->bcr[i], 0x00000000, 0);
}
}
}
printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
#endif
- cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
- sdram_size(sdram->bcr[i]),
- IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(),
+ &sdram->ram_memories[i]);
}
}
sdram->pmit = (val & 0xF8000000) | 0x07C00000;
break;
case 0x40: /* SDRAM_B0CR */
- sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000);
+ sdram_set_bcr(sdram, &sdram->bcr[0], val, sdram->cfg & 0x80000000);
break;
case 0x44: /* SDRAM_B1CR */
- sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000);
+ sdram_set_bcr(sdram, &sdram->bcr[1], val, sdram->cfg & 0x80000000);
break;
case 0x48: /* SDRAM_B2CR */
- sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000);
+ sdram_set_bcr(sdram, &sdram->bcr[2], val, sdram->cfg & 0x80000000);
break;
case 0x4C: /* SDRAM_B3CR */
- sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000);
+ sdram_set_bcr(sdram, &sdram->bcr[3], val, sdram->cfg & 0x80000000);
break;
case 0x80: /* SDRAM_TR */
sdram->tr = val & 0x018FC01F;
}
void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
+ MemoryRegion *ram_memories,
target_phys_addr_t *ram_bases,
target_phys_addr_t *ram_sizes,
int do_init)
sdram = g_malloc0(sizeof(ppc4xx_sdram_t));
sdram->irq = irq;
sdram->nbanks = nbanks;
+ sdram->ram_memories = ram_memories;
memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
memcpy(sdram->ram_bases, ram_bases,
nbanks * sizeof(target_phys_addr_t));
* must be one of a small set of sizes. The number of banks and the supported
* sizes varies by SoC. */
ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
+ MemoryRegion ram_memories[],
target_phys_addr_t ram_bases[],
target_phys_addr_t ram_sizes[],
const unsigned int sdram_bank_sizes[])
{
ram_addr_t size_left = ram_size;
+ ram_addr_t base = 0;
int i;
int j;
if (bank_size <= size_left) {
char name[32];
snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
- ram_bases[i] = qemu_ram_alloc(NULL, name, bank_size);
+ memory_region_init_ram(&ram_memories[i], NULL, name, bank_size);
+ ram_bases[i] = base;
ram_sizes[i] = bank_size;
+ base += ram_size;
size_left -= bank_size;
break;
}
MacIONVRAMState *nvr;
int bios_size;
MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem, *escc_mem;
+ MemoryRegion *escc_bar = g_new(MemoryRegion, 1);
MemoryRegion *ide_mem[3];
int ppc_boot_device;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
escc_mem = escc_init(0x80013000, pic[0x25], pic[0x24],
serial_hds[0], serial_hds[1], ESCC_CLOCK, 4);
+ memory_region_init_alias(escc_bar, "escc-bar",
+ escc_mem, 0, memory_region_size(escc_mem));
for(i = 0; i < nb_nics; i++)
pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
adb_mouse_init(&adb_bus);
macio_init(pci_bus, PCI_DEVICE_ID_APPLE_UNI_N_KEYL, 0, pic_mem,
- dbdma_mem, cuda_mem, NULL, 3, ide_mem, escc_mem);
+ dbdma_mem, cuda_mem, NULL, 3, ide_mem, escc_bar);
if (usb_enabled) {
usb_ohci_init_pci(pci_bus, -1);
MacIONVRAMState *nvr;
int bios_size;
MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem;
- MemoryRegion *escc_mem, *ide_mem[2];
+ MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1), *ide_mem[2];
uint16_t ppc_boot_device;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
void *fw_cfg;
escc_mem = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],
serial_hds[1], ESCC_CLOCK, 4);
+ memory_region_init_alias(escc_bar, "escc-bar",
+ escc_mem, 0, memory_region_size(escc_mem));
for(i = 0; i < nb_nics; i++)
pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
pmac_format_nvram_partition(nvr, 0x2000);
macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem,
- dbdma_mem, cuda_mem, nvr, 2, ide_mem, escc_mem);
+ dbdma_mem, cuda_mem, nvr, 2, ide_mem, escc_bar);
if (usb_enabled) {
usb_ohci_init_pci(pci_bus, -1);
s->reg);
}
+static void e500_pci_unmap(SysBusDevice *dev, target_phys_addr_t base)
+{
+ cpu_register_physical_memory(base + PCIE500_CFGADDR, 4,
+ IO_MEM_UNASSIGNED);
+ cpu_register_physical_memory(base + PCIE500_CFGDATA, 4,
+ IO_MEM_UNASSIGNED);
+ cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE,
+ IO_MEM_UNASSIGNED);
+}
+
#include "exec-memory.h"
static int e500_pcihost_initfn(SysBusDevice *dev)
DEVICE_LITTLE_ENDIAN);
s->reg = cpu_register_io_memory(e500_pci_reg_read, e500_pci_reg_write, s,
DEVICE_BIG_ENDIAN);
- sysbus_init_mmio_cb(dev, PCIE500_ALL_SIZE, e500_pci_map);
+ sysbus_init_mmio_cb2(dev, e500_pci_map, e500_pci_unmap);
return 0;
}
else
ch = ~value;
if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
- qemu_chr_write(s->chr, &ch, 1);
+ qemu_chr_fe_write(s->chr, &ch, 1);
break;
case ICSR0:
s->status[0] &= ~(value & 0x66);
ram_size = 32 * 1024 * 1024;
}
vga_common_init(vga, ram_size);
- vga_init(vga);
+ vga_init(vga, pci_address_space(dev));
register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write, vga);
register_ioport_write(0x3b4, 2, 1, qxl_vga_ioport_write, vga);
register_ioport_write(0x3d4, 2, 1, qxl_vga_ioport_write, vga);
typedef struct {
gic_state gic;
- int iomemtype;
+ MemoryRegion iomem;
+ MemoryRegion container;
} RealViewGICState;
-static uint32_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset)
+static uint64_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
gic_state *s = (gic_state *)opaque;
return gic_cpu_read(s, gic_get_current_cpu(), offset);
}
static void realview_gic_cpu_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
gic_state *s = (gic_state *)opaque;
gic_cpu_write(s, gic_get_current_cpu(), offset, value);
}
-static CPUReadMemoryFunc * const realview_gic_cpu_readfn[] = {
- realview_gic_cpu_read,
- realview_gic_cpu_read,
- realview_gic_cpu_read
+static const MemoryRegionOps realview_gic_cpu_ops = {
+ .read = realview_gic_cpu_read,
+ .write = realview_gic_cpu_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const realview_gic_cpu_writefn[] = {
- realview_gic_cpu_write,
- realview_gic_cpu_write,
- realview_gic_cpu_write
-};
-
-static void realview_gic_map(SysBusDevice *dev, target_phys_addr_t base)
+static void realview_gic_map_setup(RealViewGICState *s)
{
- RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev);
- cpu_register_physical_memory(base, 0x1000, s->iomemtype);
- cpu_register_physical_memory(base + 0x1000, 0x1000, s->gic.iomemtype);
+ memory_region_init(&s->container, "realview-gic-container", 0x2000);
+ memory_region_init_io(&s->iomem, &realview_gic_cpu_ops, &s->gic,
+ "realview-gic", 0x1000);
+ memory_region_add_subregion(&s->container, 0, &s->iomem);
+ memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
}
static int realview_gic_init(SysBusDevice *dev)
RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev);
gic_init(&s->gic);
- s->iomemtype = cpu_register_io_memory(realview_gic_cpu_readfn,
- realview_gic_cpu_writefn, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio_cb(dev, 0x2000, realview_gic_map);
+ realview_gic_map_setup(s);
+ sysbus_init_mmio_region(dev, &s->container);
return 0;
}
ssp.data_bits = data_bits;
ssp.stop_bits = stop_bits;
s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
- qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
+ qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
speed, parity, data_bits, stop_bits);
qemu_del_timer(s->modem_status_poll);
- if (qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
+ if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
s->poll_msl = -1;
return;
}
if (s->mcr & UART_MCR_LOOP) {
/* in loopback mode, say that we just received a char */
serial_receive1(s, &s->tsr, 1);
- } else if (qemu_chr_write(s->chr, &s->tsr, 1) != 1) {
+ } else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1) {
if ((s->tsr_retry > 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) {
s->tsr_retry++;
qemu_mod_timer(s->transmit_timer, new_xmit_ts + s->char_transmit_time);
break_enable = (val >> 6) & 1;
if (break_enable != s->last_break_enable) {
s->last_break_enable = break_enable;
- qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
+ qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
&break_enable);
}
}
if (s->poll_msl >= 0 && old_mcr != s->mcr) {
- qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
+ qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
if (val & UART_MCR_DTR)
flags |= CHR_TIOCM_DTR;
- qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
+ qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
/* Update the modem status after a one-character-send wait-time, since there may be a response
from the device/computer at the other end of the serial line */
qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time);
PCIBus *bus;
PCIDevice *dev;
qemu_irq irq[4];
- int memconfig;
+ MemoryRegion memconfig_p4;
+ MemoryRegion memconfig_a7;
+ MemoryRegion isa;
uint32_t par;
uint32_t mbr;
uint32_t iobr;
} SHPCIState;
-static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
+static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint64_t val,
+ unsigned size)
{
SHPCIState *pcic = p;
switch(addr) {
break;
case 0x1c8:
if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) {
- cpu_register_physical_memory(pcic->iobr & 0xfffc0000, 0x40000,
- IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(), &pcic->isa);
pcic->iobr = val & 0xfffc0001;
- isa_mmio_init(pcic->iobr & 0xfffc0000, 0x40000);
+ memory_region_add_subregion(get_system_memory(),
+ pcic->iobr & 0xfffc0000, &pcic->isa);
}
break;
case 0x220:
}
}
-static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr)
+static uint64_t sh_pci_reg_read (void *p, target_phys_addr_t addr,
+ unsigned size)
{
SHPCIState *pcic = p;
switch(addr) {
return 0;
}
-typedef struct {
- CPUReadMemoryFunc * const r[3];
- CPUWriteMemoryFunc * const w[3];
-} MemOp;
-
-static MemOp sh_pci_reg = {
- { NULL, NULL, sh_pci_reg_read },
- { NULL, NULL, sh_pci_reg_write },
+static const MemoryRegionOps sh_pci_reg_ops = {
+ .read = sh_pci_reg_read,
+ .write = sh_pci_reg_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
static int sh_pci_map_irq(PCIDevice *d, int irq_num)
{
SHPCIState *s = FROM_SYSBUS(SHPCIState, dev);
- cpu_register_physical_memory(P4ADDR(base), 0x224, s->memconfig);
- cpu_register_physical_memory(A7ADDR(base), 0x224, s->memconfig);
-
+ memory_region_add_subregion(get_system_memory(),
+ P4ADDR(base),
+ &s->memconfig_p4);
+ memory_region_add_subregion(get_system_memory(),
+ A7ADDR(base),
+ &s->memconfig_a7);
s->iobr = 0xfe240000;
- isa_mmio_init(s->iobr, 0x40000);
+ memory_region_add_subregion(get_system_memory(), s->iobr, &s->isa);
+}
+
+static void sh_pci_unmap(SysBusDevice *dev, target_phys_addr_t base)
+{
+ SHPCIState *s = FROM_SYSBUS(SHPCIState, dev);
+
+ memory_region_del_subregion(get_system_memory(), &s->memconfig_p4);
+ memory_region_del_subregion(get_system_memory(), &s->memconfig_a7);
+ memory_region_del_subregion(get_system_memory(), &s->isa);
}
static int sh_pci_init_device(SysBusDevice *dev)
get_system_memory(),
get_system_io(),
PCI_DEVFN(0, 0), 4);
- s->memconfig = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w,
- s, DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio_cb(dev, 0x224, sh_pci_map);
+ memory_region_init_io(&s->memconfig_p4, &sh_pci_reg_ops, s,
+ "sh_pci", 0x224);
+ memory_region_init_alias(&s->memconfig_a7, "sh_pci.2", &s->memconfig_a7,
+ 0, 0x224);
+ isa_mmio_setup(&s->isa, 0x40000);
+ sysbus_init_mmio_cb2(dev, sh_pci_map, sh_pci_unmap);
+ sysbus_init_mmio_region(dev, &s->memconfig_a7);
+ sysbus_init_mmio_region(dev, &s->isa);
s->dev = pci_create_simple(s->bus, PCI_DEVFN(0, 0), "sh_pci_host");
return 0;
}
case 0x0c: /* FTDR / TDR */
if (s->chr) {
ch = val;
- qemu_chr_write(s->chr, &ch, 1);
+ qemu_chr_fe_write(s->chr, &ch, 1);
}
s->dr = val;
s->flags &= ~SH_SERIAL_FLAG_TDE;
{
VIOsPAPRVTYDevice *dev = (VIOsPAPRVTYDevice *)sdev;
- /* FIXME: should check the qemu_chr_write() return value */
- qemu_chr_write(dev->chardev, buf, len);
+ /* FIXME: should check the qemu_chr_fe_write() return value */
+ qemu_chr_fe_write(dev->chardev, buf, len);
}
static int spapr_vty_init(VIOsPAPRDevice *sdev)
ssp.stop_bits = stop_bits;
s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
if (s->chr) {
- qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
+ qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
if (s->utcr3 & UTCR3_LBM) /* loopback */ {
strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
} else if (s->chr) {
- qemu_chr_write(s->chr, &s->tx_fifo[s->tx_start], 1);
+ qemu_chr_fe_write(s->chr, &s->tx_fifo[s->tx_start], 1);
}
s->tx_start = (s->tx_start + 1) % 8;
/* optimize later. Now, 1 byte per iteration */
while (count--) {
cpu_physical_memory_read(s->dma_tx_ptr, &ch, 1);
- qemu_chr_write(s->chr, &ch, 1);
+ qemu_chr_fe_write(s->chr, &ch, 1);
s->dma_tx_ptr++;
}
} else {
case SERIAL_DATA:
ch = value;
if (s->chr)
- qemu_chr_write(s->chr, &ch, 1);
+ qemu_chr_fe_write(s->chr, &ch, 1);
break;
case SERIAL_INT_ENABLE:
s->int_enable = value;
if (dev->mmio[n].memory) {
memory_region_del_subregion(get_system_memory(),
dev->mmio[n].memory);
+ } else if (dev->mmio[n].unmap) {
+ dev->mmio[n].unmap(dev, dev->mmio[n].addr);
} else {
cpu_register_physical_memory(dev->mmio[n].addr, dev->mmio[n].size,
IO_MEM_UNASSIGNED);
dev->mmio[n].iofunc = iofunc;
}
-void sysbus_init_mmio_cb(SysBusDevice *dev, target_phys_addr_t size,
- mmio_mapfunc cb)
+void sysbus_init_mmio_cb2(SysBusDevice *dev,
+ mmio_mapfunc cb, mmio_mapfunc unmap)
{
int n;
assert(dev->num_mmio < QDEV_MAX_MMIO);
n = dev->num_mmio++;
dev->mmio[n].addr = -1;
- dev->mmio[n].size = size;
+ dev->mmio[n].size = 0;
dev->mmio[n].cb = cb;
+ dev->mmio[n].unmap = unmap;
}
void sysbus_init_mmio_region(SysBusDevice *dev, MemoryRegion *memory)
target_phys_addr_t addr;
target_phys_addr_t size;
mmio_mapfunc cb;
+ mmio_mapfunc unmap;
ram_addr_t iofunc;
MemoryRegion *memory;
} mmio[QDEV_MAX_MMIO];
void *sysbus_new(void);
void sysbus_init_mmio(SysBusDevice *dev, target_phys_addr_t size,
ram_addr_t iofunc);
-void sysbus_init_mmio_cb(SysBusDevice *dev, target_phys_addr_t size,
- mmio_mapfunc cb);
+void sysbus_init_mmio_cb2(SysBusDevice *dev,
+ mmio_mapfunc cb, mmio_mapfunc unmap);
void sysbus_init_mmio_region(SysBusDevice *dev, MemoryRegion *memory);
void sysbus_init_irq(SysBusDevice *dev, qemu_irq *p);
void sysbus_pass_irq(SysBusDevice *dev, SysBusDevice *target);
#include "usb.h"
#include "omap.h"
#include "irq.h"
-#include "devices.h"
+#include "tusb6010.h"
struct TUSBState {
- int iomemtype[2];
+ MemoryRegion iomem[2];
qemu_irq irq;
MUSBState *musb;
QEMUTimer *otg_timer;
#define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff)
#define TUSB_PROD_TEST_RESET_VAL 0xa596
-int tusb6010_sync_io(TUSBState *s)
+MemoryRegion *tusb6010_sync_io(TUSBState *s)
{
- return s->iomemtype[0];
+ return &s->iomem[0];
}
-int tusb6010_async_io(TUSBState *s)
+MemoryRegion *tusb6010_async_io(TUSBState *s)
{
- return s->iomemtype[1];
+ return &s->iomem[1];
}
static void tusb_intr_update(TUSBState *s)
}
}
-static CPUReadMemoryFunc * const tusb_async_readfn[] = {
- tusb_async_readb,
- tusb_async_readh,
- tusb_async_readw,
-};
-
-static CPUWriteMemoryFunc * const tusb_async_writefn[] = {
- tusb_async_writeb,
- tusb_async_writeh,
- tusb_async_writew,
+static const MemoryRegionOps tusb_async_ops = {
+ .old_mmio = {
+ .read = { tusb_async_readb, tusb_async_readh, tusb_async_readw, },
+ .write = { tusb_async_writeb, tusb_async_writeh, tusb_async_writew, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void tusb_otg_tick(void *opaque)
s->mask = 0xffffffff;
s->intr = 0x00000000;
s->otg_timer_val = 0;
- s->iomemtype[1] = cpu_register_io_memory(tusb_async_readfn,
- tusb_async_writefn, s, DEVICE_NATIVE_ENDIAN);
+ memory_region_init_io(&s->iomem[1], &tusb_async_ops, s, "tusb-async",
+ UINT32_MAX);
s->irq = intr;
s->otg_timer = qemu_new_timer_ns(vm_clock, tusb_otg_tick, s);
s->pwr_timer = qemu_new_timer_ns(vm_clock, tusb_power_tick, s);
--- /dev/null
+/*
+ * tusb6010 interfaces
+ *
+ * Copyright 2011 Red Hat, Inc. and/or its affiliates
+ *
+ * Authors:
+ * Avi Kivity <avi@redhat.com>
+ *
+ * Derived from hw/devices.h.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef TUSB6010_H
+#define TUSB6010_H
+
+#include "targphys.h"
+#include "memory.h"
+
+typedef struct TUSBState TUSBState;
+TUSBState *tusb6010_init(qemu_irq intr);
+MemoryRegion *tusb6010_sync_io(TUSBState *s);
+MemoryRegion *tusb6010_async_io(TUSBState *s);
+void tusb6010_power(TUSBState *s, int on);
+
+#endif
int flags;
uint8_t ret;
- if (qemu_chr_ioctl(s->cs, CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP)
+ if (qemu_chr_fe_ioctl(s->cs, CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP)
return FTDI_CTS|FTDI_DSR|FTDI_RLSD;
ret = 0;
case DeviceOutVendor | FTDI_SET_MDM_CTRL:
{
static int flags;
- qemu_chr_ioctl(s->cs,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
+ qemu_chr_fe_ioctl(s->cs,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
if (value & FTDI_SET_RTS) {
if (value & FTDI_RTS)
flags |= CHR_TIOCM_RTS;
else
flags &= ~CHR_TIOCM_DTR;
}
- qemu_chr_ioctl(s->cs,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
+ qemu_chr_fe_ioctl(s->cs,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
break;
}
case DeviceOutVendor | FTDI_SET_FLOW_CTRL:
divisor = 1;
s->params.speed = (48000000 / 2) / (8 * divisor + subdivisor8);
- qemu_chr_ioctl(s->cs, CHR_IOCTL_SERIAL_SET_PARAMS, &s->params);
+ qemu_chr_fe_ioctl(s->cs, CHR_IOCTL_SERIAL_SET_PARAMS, &s->params);
break;
}
case DeviceOutVendor | FTDI_SET_DATA:
DPRINTF("unsupported stop bits %d\n", value & FTDI_STOP);
goto fail;
}
- qemu_chr_ioctl(s->cs, CHR_IOCTL_SERIAL_SET_PARAMS, &s->params);
+ qemu_chr_fe_ioctl(s->cs, CHR_IOCTL_SERIAL_SET_PARAMS, &s->params);
/* TODO: TX ON/OFF */
break;
case DeviceInVendor | FTDI_GET_MDM_ST:
goto fail;
for (i = 0; i < p->iov.niov; i++) {
iov = p->iov.iov + i;
- qemu_chr_write(s->cs, iov->iov_base, iov->iov_len);
+ qemu_chr_fe_write(s->cs, iov->iov_base, iov->iov_len);
}
break;
{
USBSerialState *s = (USBSerialState *)dev;
- qemu_chr_close(s->cs);
+ qemu_chr_delete(s->cs);
}
static int usb_serial_can_read(void *opaque)
filename++;
snprintf(label, sizeof(label), "usbserial%d", index++);
- cdrv = qemu_chr_open(label, filename, NULL);
+ cdrv = qemu_chr_new(label, filename, NULL);
if (!cdrv)
return NULL;
USBDevice *dev;
CharDriverState *cdrv;
- cdrv = qemu_chr_open("braille", "braille", NULL);
+ cdrv = qemu_chr_new("braille", "braille", NULL);
if (!cdrv)
return NULL;
SysBusDevice busdev;
qemu_irq irq[4];
int realview;
- int mem_config;
+ MemoryRegion mem_config;
+ MemoryRegion mem_config2;
+ MemoryRegion isa;
} PCIVPBState;
static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
return addr & 0xffffff;
}
-static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void pci_vpb_config_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
- pci_data_write(opaque, vpb_pci_config_addr (addr), val, 1);
+ pci_data_write(opaque, vpb_pci_config_addr(addr), val, size);
}
-static void pci_vpb_config_writew (void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- pci_data_write(opaque, vpb_pci_config_addr (addr), val, 2);
-}
-
-static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- pci_data_write(opaque, vpb_pci_config_addr (addr), val, 4);
-}
-
-static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr)
-{
- uint32_t val;
- val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1);
- return val;
-}
-
-static uint32_t pci_vpb_config_readw (void *opaque, target_phys_addr_t addr)
-{
- uint32_t val;
- val = pci_data_read(opaque, vpb_pci_config_addr (addr), 2);
- return val;
-}
-
-static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr)
+static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
uint32_t val;
- val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4);
+ val = pci_data_read(opaque, vpb_pci_config_addr(addr), size);
return val;
}
-static CPUWriteMemoryFunc * const pci_vpb_config_write[] = {
- &pci_vpb_config_writeb,
- &pci_vpb_config_writew,
- &pci_vpb_config_writel,
-};
-
-static CPUReadMemoryFunc * const pci_vpb_config_read[] = {
- &pci_vpb_config_readb,
- &pci_vpb_config_readw,
- &pci_vpb_config_readl,
+static const MemoryRegionOps pci_vpb_config_ops = {
+ .read = pci_vpb_config_read,
+ .write = pci_vpb_config_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
qemu_set_irq(pic[irq_num], level);
}
+
static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base)
{
PCIVPBState *s = (PCIVPBState *)dev;
/* Selfconfig area. */
- cpu_register_physical_memory(base + 0x01000000, 0x1000000, s->mem_config);
+ memory_region_add_subregion(get_system_memory(), base + 0x01000000,
+ &s->mem_config);
+ /* Normal config area. */
+ memory_region_add_subregion(get_system_memory(), base + 0x02000000,
+ &s->mem_config2);
+
+ if (s->realview) {
+ /* IO memory area. */
+ memory_region_add_subregion(get_system_memory(), base + 0x03000000,
+ &s->isa);
+ }
+}
+
+static void pci_vpb_unmap(SysBusDevice *dev, target_phys_addr_t base)
+{
+ PCIVPBState *s = (PCIVPBState *)dev;
+ /* Selfconfig area. */
+ memory_region_del_subregion(get_system_memory(), &s->mem_config);
/* Normal config area. */
- cpu_register_physical_memory(base + 0x02000000, 0x1000000, s->mem_config);
+ memory_region_del_subregion(get_system_memory(), &s->mem_config2);
if (s->realview) {
/* IO memory area. */
- isa_mmio_init(base + 0x03000000, 0x00100000);
+ memory_region_del_subregion(get_system_memory(), &s->isa);
}
}
/* ??? Register memory space. */
- s->mem_config = cpu_register_io_memory(pci_vpb_config_read,
- pci_vpb_config_write, bus,
- DEVICE_LITTLE_ENDIAN);
- sysbus_init_mmio_cb(dev, 0x04000000, pci_vpb_map);
+ memory_region_init_io(&s->mem_config, &pci_vpb_config_ops, bus,
+ "pci-vpb-selfconfig", 0x1000000);
+ memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, bus,
+ "pci-vpb-config", 0x1000000);
+ if (s->realview) {
+ isa_mmio_setup(&s->isa, 0x0100000);
+ }
+
+ sysbus_init_mmio_cb2(dev, pci_vpb_map, pci_vpb_unmap);
pci_create_simple(bus, -1, "versatile_pci_host");
return 0;
#include "vga_int.h"
#include "pixel_ops.h"
#include "qemu-timer.h"
-#include "exec-memory.h"
typedef struct ISAVGAMMState {
VGACommonState vga;
};
static void vga_mm_init(ISAVGAMMState *s, target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift)
+ target_phys_addr_t ctrl_base, int it_shift,
+ MemoryRegion *address_space)
{
MemoryRegion *s_ioport_ctrl, *vga_io_memory;
vmstate_register(NULL, 0, &vmstate_vga_common, s);
- memory_region_add_subregion(get_system_memory(), ctrl_base, s_ioport_ctrl);
+ memory_region_add_subregion(address_space, ctrl_base, s_ioport_ctrl);
s->vga.bank_offset = 0;
- memory_region_add_subregion(get_system_memory(),
+ memory_region_add_subregion(address_space,
vram_base + 0x000a0000, vga_io_memory);
memory_region_set_coalescing(vga_io_memory);
}
int isa_vga_mm_init(target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift)
+ target_phys_addr_t ctrl_base, int it_shift,
+ MemoryRegion *address_space)
{
ISAVGAMMState *s;
s = g_malloc0(sizeof(*s));
vga_common_init(&s->vga, VGA_RAM_SIZE);
- vga_mm_init(s, vram_base, ctrl_base, it_shift);
+ vga_mm_init(s, vram_base, ctrl_base, it_shift, address_space);
s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
s->vga.screen_dump, s->vga.text_update, s);
- vga_init_vbe(&s->vga);
+ vga_init_vbe(&s->vga, address_space);
return 0;
}
#include "pixel_ops.h"
#include "qemu-timer.h"
#include "loader.h"
-#include "exec-memory.h"
typedef struct ISAVGAState {
ISADevice dev;
vga_common_init(s, VGA_RAM_SIZE);
vga_io_memory = vga_init_io(s);
- memory_region_add_subregion_overlap(get_system_memory(),
+ memory_region_add_subregion_overlap(isa_address_space(dev),
isa_mem_base + 0x000a0000,
vga_io_memory, 1);
memory_region_set_coalescing(vga_io_memory);
s->ds = graphic_console_init(s->update, s->invalidate,
s->screen_dump, s->text_update, s);
- vga_init_vbe(s);
+ vga_init_vbe(s, isa_address_space(dev));
/* ROM BIOS */
rom_add_vga(VGABIOS_FILENAME);
return 0;
// vga + console init
vga_common_init(s, VGA_RAM_SIZE);
- vga_init(s);
+ vga_init(s, pci_address_space(dev));
s->ds = graphic_console_init(s->update, s->invalidate,
s->screen_dump, s->text_update, s);
if (!dev->rom_bar) {
/* compatibility with pc-0.13 and older */
- vga_init_vbe(s);
+ vga_init_vbe(s, pci_address_space(dev));
}
return 0;
#include "vga_int.h"
#include "pixel_ops.h"
#include "qemu-timer.h"
-#include "exec-memory.h"
//#define DEBUG_VGA
//#define DEBUG_VGA_MEM
static char *screen_dump_filename;
static DisplayChangeListener *screen_dump_dcl;
+static void vga_update_memory_access(VGACommonState *s)
+{
+ MemoryRegion *region, *old_region = s->chain4_alias;
+ target_phys_addr_t base, offset, size;
+
+ s->chain4_alias = NULL;
+
+ if ((s->sr[0x02] & 0xf) == 0xf && s->sr[0x04] & 0x08) {
+ offset = 0;
+ switch ((s->gr[6] >> 2) & 3) {
+ case 0:
+ base = 0xa0000;
+ size = 0x20000;
+ break;
+ case 1:
+ base = 0xa0000;
+ size = 0x10000;
+ offset = s->bank_offset;
+ break;
+ case 2:
+ base = 0xb0000;
+ size = 0x8000;
+ break;
+ case 3:
+ base = 0xb8000;
+ size = 0x8000;
+ break;
+ }
+ region = g_malloc(sizeof(*region));
+ memory_region_init_alias(region, "vga.chain4", &s->vram, offset, size);
+ memory_region_add_subregion_overlap(s->legacy_address_space, base,
+ region, 2);
+ s->chain4_alias = region;
+ }
+ if (old_region) {
+ memory_region_del_subregion(s->legacy_address_space, old_region);
+ memory_region_destroy(old_region);
+ g_free(old_region);
+ s->plane_updated = 0xf;
+ }
+}
+
static void vga_dumb_update_retrace_info(VGACommonState *s)
{
(void) s;
#endif
s->sr[s->sr_index] = val & sr_mask[s->sr_index];
if (s->sr_index == 1) s->update_retrace_info(s);
+ vga_update_memory_access(s);
break;
case 0x3c7:
s->dac_read_index = val;
printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
#endif
s->gr[s->gr_index] = val & gr_mask[s->gr_index];
+ vga_update_memory_access(s);
break;
case 0x3b4:
case 0x3d4:
}
s->vbe_regs[s->vbe_index] = val;
s->bank_offset = (val << 16);
+ vga_update_memory_access(s);
break;
case VBE_DISPI_INDEX_ENABLE:
if ((val & VBE_DISPI_ENABLED) &&
}
s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
s->vbe_regs[s->vbe_index] = val;
+ vga_update_memory_access(s);
break;
case VBE_DISPI_INDEX_VIRT_WIDTH:
{
s->font_offsets[1] = offset;
full_update = 1;
}
- if (s->plane_updated & (1 << 2)) {
+ if (s->plane_updated & (1 << 2) || s->chain4_alias) {
/* if the plane 2 was modified since the last display, it
indicates the font may have been modified */
s->plane_updated = 0;
memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA);
}
-void vga_dirty_log_restart(VGACommonState *s)
-{
- vga_dirty_log_stop(s);
- vga_dirty_log_start(s);
-}
-
/*
* graphic modes
*/
memset(&s->retrace_info, 0, sizeof (s->retrace_info));
break;
}
+ vga_update_memory_access(s);
}
static void vga_reset(void *opaque)
return vga_mem;
}
-void vga_init(VGACommonState *s)
+void vga_init(VGACommonState *s, MemoryRegion *address_space)
{
MemoryRegion *vga_io_memory;
s->bank_offset = 0;
+ s->legacy_address_space = address_space;
+
vga_io_memory = vga_init_io(s);
- memory_region_add_subregion_overlap(get_system_memory(),
+ memory_region_add_subregion_overlap(address_space,
isa_mem_base + 0x000a0000,
vga_io_memory,
1);
memory_region_set_coalescing(vga_io_memory);
}
-void vga_init_vbe(VGACommonState *s)
+void vga_init_vbe(VGACommonState *s, MemoryRegion *system_memory)
{
#ifdef CONFIG_BOCHS_VBE
/* XXX: use optimized standard vga accesses */
- memory_region_add_subregion(get_system_memory(),
+ memory_region_add_subregion(system_memory,
VBE_DISPI_LFB_PHYSICAL_ADDRESS,
&s->vram);
s->vbe_mapped = 1;
typedef void (* vga_update_retrace_info_fn)(struct VGACommonState *s);
typedef struct VGACommonState {
+ MemoryRegion *legacy_address_space;
uint8_t *vram_ptr;
MemoryRegion vram;
uint32_t vram_size;
uint32_t latch;
- uint32_t lfb_vram_mapped; /* whether 0xa0000 is mapped as ram */
+ MemoryRegion *chain4_alias;
uint8_t sr_index;
uint8_t sr[256];
uint8_t gr_index;
int dac_8bit;
uint8_t palette[768];
int32_t bank_offset;
- MemoryRegion *vga_io_memory;
int (*get_bpp)(struct VGACommonState *s);
void (*get_offsets)(struct VGACommonState *s,
uint32_t *pline_offset,
}
void vga_common_init(VGACommonState *s, int vga_ram_size);
-void vga_init(VGACommonState *s);
+void vga_init(VGACommonState *s, MemoryRegion *address_space);
MemoryRegion *vga_init_io(VGACommonState *s);
void vga_common_reset(VGACommonState *s);
void vga_dirty_log_start(VGACommonState *s);
void vga_dirty_log_stop(VGACommonState *s);
-void vga_dirty_log_restart(VGACommonState *s);
extern const VMStateDescription vmstate_vga_common;
uint32_t vga_ioport_read(void *opaque, uint32_t addr);
unsigned int color_xor);
int vga_ioport_invalid(VGACommonState *s, uint32_t addr);
-void vga_init_vbe(VGACommonState *s);
+void vga_init_vbe(VGACommonState *s, MemoryRegion *address_space);
extern const uint8_t sr_mask[8];
extern const uint8_t gr_mask[16];
VirtConsole *vcon = DO_UPCAST(VirtConsole, port, port);
ssize_t ret;
- ret = qemu_chr_write(vcon->chr, buf, len);
+ ret = qemu_chr_fe_write(vcon->chr, buf, len);
trace_virtio_console_flush_buf(port->id, len, ret);
if (ret < 0) {
{
VirtConsole *vcon = DO_UPCAST(VirtConsole, port, port);
- qemu_chr_guest_open(vcon->chr);
+ qemu_chr_fe_open(vcon->chr);
}
/* Callback function that's called when the guest closes the port */
{
VirtConsole *vcon = DO_UPCAST(VirtConsole, port, port);
- qemu_chr_guest_close(vcon->chr);
+ qemu_chr_fe_close(vcon->chr);
}
/* Readiness of the guest to accept data on a port */
#include "pci.h"
#include "vmware_vga.h"
-#define VERBOSE
-#undef DIRECT_VRAM
+#undef VERBOSE
#define HW_RECT_ACCEL
#define HW_FILL_ACCEL
#define HW_MOUSE_ACCEL
static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
int x, int y, int w, int h)
{
-#ifndef DIRECT_VRAM
int line;
int bypl;
int width;
for (; line > 0; line --, src += bypl, dst += bypl)
memcpy(dst, src, width);
-#endif
dpy_update(s->vga.ds, x, y, w, h);
}
static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
{
-#ifndef DIRECT_VRAM
- memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, s->bypp * s->width * s->height);
-#endif
-
+ memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr,
+ s->bypp * s->width * s->height);
dpy_update(s->vga.ds, 0, 0, s->width, s->height);
}
-#ifdef DIRECT_VRAM
-# define vmsvga_update_rect_delayed vmsvga_update_rect
-#else
static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
int x, int y, int w, int h)
{
rect->w = w;
rect->h = h;
}
-#endif
static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
{
static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
int x0, int y0, int x1, int y1, int w, int h)
{
-# ifdef DIRECT_VRAM
- uint8_t *vram = ds_get_data(s->ds);
-# else
uint8_t *vram = s->vga.vram_ptr;
-# endif
int bypl = s->bypp * s->width;
int width = s->bypp * w;
int line = h;
uint8_t *ptr[2];
-# ifdef DIRECT_VRAM
- if (s->ds->dpy_copy)
- qemu_console_copy(s->ds, x0, y0, x1, y1, w, h);
- else
-# endif
- {
- if (y1 > y0) {
- ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
- ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
- for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl)
- memmove(ptr[1], ptr[0], width);
- } else {
- ptr[0] = vram + s->bypp * x0 + bypl * y0;
- ptr[1] = vram + s->bypp * x1 + bypl * y1;
- for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl)
- memmove(ptr[1], ptr[0], width);
+ if (y1 > y0) {
+ ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
+ ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
+ for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) {
+ memmove(ptr[1], ptr[0], width);
+ }
+ } else {
+ ptr[0] = vram + s->bypp * x0 + bypl * y0;
+ ptr[1] = vram + s->bypp * x1 + bypl * y1;
+ for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) {
+ memmove(ptr[1], ptr[0], width);
}
}
static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
uint32_t c, int x, int y, int w, int h)
{
-# ifdef DIRECT_VRAM
- uint8_t *vram = ds_get_data(s->ds);
-# else
uint8_t *vram = s->vga.vram_ptr;
-# endif
int bypp = s->bypp;
int bypl = bypp * s->width;
int width = bypp * w;
uint8_t *src;
uint8_t col[4];
-# ifdef DIRECT_VRAM
- if (s->ds->dpy_fill)
- s->ds->dpy_fill(s->ds, x, y, w, h, c);
- else
-# endif
- {
- col[0] = c;
- col[1] = c >> 8;
- col[2] = c >> 16;
- col[3] = c >> 24;
-
- if (line --) {
- dst = fst;
- src = col;
- for (column = width; column > 0; column --) {
- *(dst ++) = *(src ++);
- if (src - col == bypp)
- src = col;
- }
- dst = fst;
- for (; line > 0; line --) {
- dst += bypl;
- memcpy(dst, fst, width);
+ col[0] = c;
+ col[1] = c >> 8;
+ col[2] = c >> 16;
+ col[3] = c >> 24;
+
+ if (line--) {
+ dst = fst;
+ src = col;
+ for (column = width; column > 0; column--) {
+ *(dst++) = *(src++);
+ if (src - col == bypp) {
+ src = col;
}
}
+ dst = fst;
+ for (; line > 0; line--) {
+ dst += bypl;
+ memcpy(dst, fst, width);
+ }
}
vmsvga_update_rect_delayed(s, x, y, w, h);
}
}
-static void vmsvga_reset(struct vmsvga_state_s *s)
+static void vmsvga_reset(DeviceState *dev)
{
+ struct pci_vmsvga_state_s *pci =
+ DO_UPCAST(struct pci_vmsvga_state_s, card.qdev, dev);
+ struct vmsvga_state_s *s = &pci->chip;
+
s->index = 0;
s->enable = 0;
s->config = 0;
s->width = -1;
s->height = -1;
s->svgaid = SVGA_ID;
- s->depth = ds_get_bits_per_pixel(s->vga.ds);
- s->bypp = ds_get_bytes_per_pixel(s->vga.ds);
s->cursor.on = 0;
s->redraw_fifo_first = 0;
s->redraw_fifo_last = 0;
- switch (s->depth) {
- case 8:
- s->wred = 0x00000007;
- s->wgreen = 0x00000038;
- s->wblue = 0x000000c0;
- break;
- case 15:
- s->wred = 0x0000001f;
- s->wgreen = 0x000003e0;
- s->wblue = 0x00007c00;
- break;
- case 16:
- s->wred = 0x0000001f;
- s->wgreen = 0x000007e0;
- s->wblue = 0x0000f800;
- break;
- case 24:
- s->wred = 0x00ff0000;
- s->wgreen = 0x0000ff00;
- s->wblue = 0x000000ff;
- break;
- case 32:
- s->wred = 0x00ff0000;
- s->wgreen = 0x0000ff00;
- s->wblue = 0x000000ff;
- break;
- }
s->syncing = 0;
vga_dirty_log_start(&s->vga);
s->vga.text_update(&s->vga, chardata);
}
-#ifdef DIRECT_VRAM
-static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
-{
- struct vmsvga_state_s *s = opaque;
- if (addr < s->fb_size)
- return *(uint8_t *) (ds_get_data(s->ds) + addr);
- else
- return *(uint8_t *) (s->vram_ptr + addr);
-}
-
-static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
-{
- struct vmsvga_state_s *s = opaque;
- if (addr < s->fb_size)
- return *(uint16_t *) (ds_get_data(s->ds) + addr);
- else
- return *(uint16_t *) (s->vram_ptr + addr);
-}
-
-static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
-{
- struct vmsvga_state_s *s = opaque;
- if (addr < s->fb_size)
- return *(uint32_t *) (ds_get_data(s->ds) + addr);
- else
- return *(uint32_t *) (s->vram_ptr + addr);
-}
-
-static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
- uint32_t value)
-{
- struct vmsvga_state_s *s = opaque;
- if (addr < s->fb_size)
- *(uint8_t *) (ds_get_data(s->ds) + addr) = value;
- else
- *(uint8_t *) (s->vram_ptr + addr) = value;
-}
-
-static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
- uint32_t value)
-{
- struct vmsvga_state_s *s = opaque;
- if (addr < s->fb_size)
- *(uint16_t *) (ds_get_data(s->ds) + addr) = value;
- else
- *(uint16_t *) (s->vram_ptr + addr) = value;
-}
-
-static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
- uint32_t value)
-{
- struct vmsvga_state_s *s = opaque;
- if (addr < s->fb_size)
- *(uint32_t *) (ds_get_data(s->ds) + addr) = value;
- else
- *(uint32_t *) (s->vram_ptr + addr) = value;
-}
-
-static const MemoryRegionOps vmsvga_vram_io_ops = {
- .old_mmio = {
- .read = {
- vmsvga_vram_readb,
- vmsvga_vram_readw,
- vmsvga_vram_readl,
- },
- .write = {
- vmsvga_vram_writeb,
- vmsvga_vram_writew,
- vmsvga_vram_writel,
- },
- },
- .endianness = DEVICE_NATIVE_ENDIAN,
-}
-
-#endif
-
static int vmsvga_post_load(void *opaque, int version_id)
{
struct vmsvga_state_s *s = opaque;
}
};
-static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size)
+static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size,
+ MemoryRegion *address_space)
{
s->scratch_size = SVGA_SCRATCH_SIZE;
s->scratch = g_malloc(s->scratch_size * 4);
s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
vga_common_init(&s->vga, vga_ram_size);
- vga_init(&s->vga);
+ vga_init(&s->vga, address_space);
vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
- vmsvga_reset(s);
+ s->depth = ds_get_bits_per_pixel(s->vga.ds);
+ s->bypp = ds_get_bytes_per_pixel(s->vga.ds);
+ switch (s->depth) {
+ case 8:
+ s->wred = 0x00000007;
+ s->wgreen = 0x00000038;
+ s->wblue = 0x000000c0;
+ break;
+ case 15:
+ s->wred = 0x0000001f;
+ s->wgreen = 0x000003e0;
+ s->wblue = 0x00007c00;
+ break;
+ case 16:
+ s->wred = 0x0000001f;
+ s->wgreen = 0x000007e0;
+ s->wblue = 0x0000f800;
+ break;
+ case 24:
+ s->wred = 0x00ff0000;
+ s->wgreen = 0x0000ff00;
+ s->wblue = 0x000000ff;
+ break;
+ case 32:
+ s->wred = 0x00ff0000;
+ s->wgreen = 0x0000ff00;
+ s->wblue = 0x000000ff;
+ break;
+ }
}
static uint64_t vmsvga_io_read(void *opaque, target_phys_addr_t addr,
DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
MemoryRegion *iomem;
-#ifdef DIRECT_VRAM
- DirectMem *directmem = g_malloc(sizeof(*directmem));
-
- iomem = &directmem->mr;
- memory_region_init_io(iomem, &vmsvga_vram_io_ops, &s->chip, "vmsvga",
- memory_region_size(&s->chip.vga.vram));
-#else
iomem = &s->chip.vga.vram;
-#endif
-
- vga_dirty_log_restart(&s->chip.vga);
s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */
"vmsvga-io", 0x10);
pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
- vmsvga_init(&s->chip, VGA_RAM_SIZE);
+ vmsvga_init(&s->chip, VGA_RAM_SIZE, pci_address_space(dev));
pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, iomem);
pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
if (!dev->rom_bar) {
/* compatibility with pc-0.13 and older */
- vga_init_vbe(&s->chip.vga);
+ vga_init_vbe(&s->chip.vga, pci_address_space(dev));
}
return 0;
.qdev.name = "vmware-svga",
.qdev.size = sizeof(struct pci_vmsvga_state_s),
.qdev.vmsd = &vmstate_vmware_vga,
+ .qdev.reset = vmsvga_reset,
.no_hotplug = 1,
.init = pci_vmsvga_initfn,
.romfile = "vgabios-vmware.bin",
size = con->buffer.size - con->buffer.consumed;
if (con->chr)
- len = qemu_chr_write(con->chr, con->buffer.data + con->buffer.consumed,
+ len = qemu_chr_fe_write(con->chr, con->buffer.data + con->buffer.consumed,
size);
else
len = size;
con->chr = serial_hds[con->xendev.dev];
} else {
snprintf(label, sizeof(label), "xencons%d", con->xendev.dev);
- con->chr = qemu_chr_open(label, output, NULL);
+ con->chr = qemu_chr_new(label, output, NULL);
}
xenstore_store_pv_console_info(con->xendev.dev, con->chr);
-
-/* OPB Interrupt Controller. */
-qemu_irq *microblaze_pic_init_cpu(CPUState *env);
+#include "qemu-common.h"
+#include "net.h"
static inline DeviceState *
xilinx_intc_create(target_phys_addr_t base, qemu_irq irq, int kind_of_intr)
case R_TX:
if (s->chr)
- qemu_chr_write(s->chr, &ch, 1);
+ qemu_chr_fe_write(s->chr, &ch, 1);
s->regs[addr] = value;
libcacard.lib-y=$(addsuffix .lo,$(basename $(libcacard-y)))
vscclient: $(libcacard-y) $(QEMU_OBJS) vscclient.o
- $(call quiet-command,$(CC) $(libcacard_libs) $(LIBS) -lrt -o $@ $^," LINK $@")
+ $(call quiet-command,$(CC) -o $@ $^ $(libcacard_libs) $(LIBS) -lrt," LINK $@")
clean:
rm -f *.o */*.o *.d */*.d *.a */*.a *~ */*~ vscclient *.lo .libs/* *.la *.pc
@echo "libtool is missing, please install and rerun configure"; exit 1
else
libcacard.la: $(libcacard.lib-y) $(QEMU_OBJS_LIB)
- $(call quiet-command,libtool --mode=link --quiet --tag=CC $(CC) $(libcacard_libs) -lrt -rpath $(libdir) -o $@ $^," lt LINK $@")
+ $(call quiet-command,$(LIBTOOL) --mode=link --quiet --tag=CC $(CC) -rpath $(libdir) -o $@ $^ $(libcacard_libs) -lrt," lt LINK $@")
libcacard.pc: $(libcacard_srcpath)/libcacard.pc.in
sed -e 's|@LIBDIR@|$(libdir)|' \
$(INSTALL_DIR) "$(DESTDIR)$(libdir)/pkgconfig"
$(INSTALL_DIR) "$(DESTDIR)$(libcacard_includedir)"
$(INSTALL_DIR) "$(DESTDIR)$(bindir)"
- libtool --mode=install $(INSTALL_PROG) vscclient "$(DESTDIR)$(bindir)"
- libtool --mode=install $(INSTALL_PROG) libcacard.la "$(DESTDIR)$(libdir)"
- libtool --mode=install $(INSTALL_DATA) libcacard.pc "$(DESTDIR)$(libdir)/pkgconfig"
+ $(LIBTOOL) --mode=install $(INSTALL_PROG) vscclient "$(DESTDIR)$(bindir)"
+ $(LIBTOOL) --mode=install $(INSTALL_PROG) libcacard.la "$(DESTDIR)$(libdir)"
+ $(LIBTOOL) --mode=install $(INSTALL_DATA) libcacard.pc "$(DESTDIR)$(libdir)/pkgconfig"
for inc in *.h; do \
- libtool --mode=install $(INSTALL_DATA) $(libcacard_srcpath)/$$inc "$(DESTDIR)$(libcacard_includedir)"; \
+ $(LIBTOOL) --mode=install $(INSTALL_DATA) $(libcacard_srcpath)/$$inc "$(DESTDIR)$(libcacard_includedir)"; \
done
endif
env->iflags &= ~(IMM_FLAG | D_FLAG);
switch (env->sregs[SR_ESR] & 31) {
+ case ESR_EC_DIVZERO:
+ info.si_signo = SIGFPE;
+ info.si_errno = 0;
+ info.si_code = TARGET_FPE_FLTDIV;
+ info._sifields._sigfault._addr = 0;
+ queue_signal(env, info.si_signo, &info);
+ break;
case ESR_EC_FPU:
info.si_signo = SIGFPE;
info.si_errno = 0;
*data = ((uint64_t)1 << (width * 8)) - 1;
if (mrp) {
- *data = mrp->read(mr->opaque, offset - mrp->offset);
+ *data = mrp->read(mr->opaque, offset);
}
return;
}
const MemoryRegionPortio *mrp = find_portio(mr, offset, width, true);
if (mrp) {
- mrp->write(mr->opaque, offset - mrp->offset, data);
+ mrp->write(mr->opaque, offset, data);
}
return;
}
|| offset + subregion->size <= other->offset) {
continue;
}
+#if 0
printf("warning: subregion collision %llx/%llx vs %llx/%llx\n",
(unsigned long long)offset,
(unsigned long long)subregion->size,
(unsigned long long)other->offset,
(unsigned long long)other->size);
+#endif
}
QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
if (subregion->priority >= other->priority) {
void monitor_flush(Monitor *mon)
{
if (mon && mon->outbuf_index != 0 && !mon->mux_out) {
- qemu_chr_write(mon->chr, mon->outbuf, mon->outbuf_index);
+ qemu_chr_fe_write(mon->chr, mon->outbuf, mon->outbuf_index);
mon->outbuf_index = 0;
}
}
mon_fd_t *monfd;
int fd;
- fd = qemu_chr_get_msgfd(mon->chr);
+ fd = qemu_chr_fe_get_msgfd(mon->chr);
if (fd == -1) {
qerror_report(QERR_FD_NOT_SUPPLIED);
return -1;
/* Control mode requires special handlers */
qemu_chr_add_handlers(chr, monitor_can_read, monitor_control_read,
monitor_control_event, mon);
- qemu_chr_set_echo(chr, true);
+ qemu_chr_fe_set_echo(chr, true);
} else {
qemu_chr_add_handlers(chr, monitor_can_read, monitor_read,
monitor_event, mon);
fwd = g_malloc(sizeof(struct GuestFwd));
snprintf(buf, sizeof(buf), "guestfwd.tcp.%d", port);
- fwd->hd = qemu_chr_open(buf, p, NULL);
+ fwd->hd = qemu_chr_new(buf, p, NULL);
if (!fwd->hd) {
error_report("could not open guest forwarding device '%s'", buf);
g_free(fwd);
}
}
-int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len)
+int qemu_chr_fe_write(CharDriverState *s, const uint8_t *buf, int len)
{
return s->chr_write(s, buf, len);
}
-int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg)
+int qemu_chr_fe_ioctl(CharDriverState *s, int cmd, void *arg)
{
if (!s->chr_ioctl)
return -ENOTSUP;
return s->chr_ioctl(s, cmd, arg);
}
-int qemu_chr_can_read(CharDriverState *s)
+int qemu_chr_be_can_write(CharDriverState *s)
{
if (!s->chr_can_read)
return 0;
return s->chr_can_read(s->handler_opaque);
}
-void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len)
+void qemu_chr_be_write(CharDriverState *s, uint8_t *buf, int len)
{
s->chr_read(s->handler_opaque, buf, len);
}
-int qemu_chr_get_msgfd(CharDriverState *s)
+int qemu_chr_fe_get_msgfd(CharDriverState *s)
{
return s->get_msgfd ? s->get_msgfd(s) : -1;
}
s->chr_accept_input(s);
}
-void qemu_chr_printf(CharDriverState *s, const char *fmt, ...)
+void qemu_chr_fe_printf(CharDriverState *s, const char *fmt, ...)
{
char buf[READ_BUF_LEN];
va_list ap;
va_start(ap, fmt);
vsnprintf(buf, sizeof(buf), fmt, ap);
- qemu_chr_write(s, (uint8_t *)buf, strlen(buf));
+ qemu_chr_fe_write(s, (uint8_t *)buf, strlen(buf));
va_end(ap);
}
-void qemu_chr_send_event(CharDriverState *s, int event)
-{
- if (s->chr_send_event)
- s->chr_send_event(s, event);
-}
-
void qemu_chr_add_handlers(CharDriverState *s,
IOCanReadHandler *fd_can_read,
IOReadHandler *fd_read,
CharDriverState *chr = opaque;
FDCharDriver *s = chr->opaque;
- s->max_size = qemu_chr_can_read(chr);
+ s->max_size = qemu_chr_be_can_write(chr);
return s->max_size;
}
return;
}
if (size > 0) {
- qemu_chr_read(chr, buf, size);
+ qemu_chr_be_write(chr, buf, size);
}
}
CharDriverState *chr = opaque;
/* try to flush the queue if needed */
- if (term_fifo_size != 0 && qemu_chr_can_read(chr) > 0) {
- qemu_chr_read(chr, term_fifo, 1);
+ if (term_fifo_size != 0 && qemu_chr_be_can_write(chr) > 0) {
+ qemu_chr_be_write(chr, term_fifo, 1);
term_fifo_size = 0;
}
/* see if we can absorb more chars */
return;
}
if (size > 0) {
- if (qemu_chr_can_read(chr) > 0) {
- qemu_chr_read(chr, buf, 1);
+ if (qemu_chr_be_can_write(chr) > 0) {
+ qemu_chr_be_write(chr, buf, 1);
} else if (term_fifo_size == 0) {
term_fifo[term_fifo_size++] = buf[0];
}
stdio_nb_clients++;
stdio_allow_signal = qemu_opt_get_bool(opts, "signal",
display_type != DT_NOGRAPHIC);
- qemu_chr_set_echo(chr, false);
+ qemu_chr_fe_set_echo(chr, false);
*_chr = chr;
return 0;
CharDriverState *chr = opaque;
PtyCharDriver *s = chr->opaque;
- s->read_bytes = qemu_chr_can_read(chr);
+ s->read_bytes = qemu_chr_be_can_write(chr);
return s->read_bytes;
}
}
if (size > 0) {
pty_chr_state(chr, 1);
- qemu_chr_read(chr, buf, size);
+ qemu_chr_be_write(chr, buf, size);
}
}
{
WinCharState *s = chr->opaque;
- s->max_size = qemu_chr_can_read(chr);
+ s->max_size = qemu_chr_be_can_write(chr);
return s->max_size;
}
}
if (size > 0) {
- qemu_chr_read(chr, buf, size);
+ qemu_chr_be_write(chr, buf, size);
}
}
CharDriverState *chr = opaque;
NetCharDriver *s = chr->opaque;
- s->max_size = qemu_chr_can_read(chr);
+ s->max_size = qemu_chr_be_can_write(chr);
/* If there were any stray characters in the queue process them
* first
*/
while (s->max_size > 0 && s->bufptr < s->bufcnt) {
- qemu_chr_read(chr, &s->buf[s->bufptr], 1);
+ qemu_chr_be_write(chr, &s->buf[s->bufptr], 1);
s->bufptr++;
- s->max_size = qemu_chr_can_read(chr);
+ s->max_size = qemu_chr_be_can_write(chr);
}
return s->max_size;
}
s->bufptr = 0;
while (s->max_size > 0 && s->bufptr < s->bufcnt) {
- qemu_chr_read(chr, &s->buf[s->bufptr], 1);
+ qemu_chr_be_write(chr, &s->buf[s->bufptr], 1);
s->bufptr++;
- s->max_size = qemu_chr_can_read(chr);
+ s->max_size = qemu_chr_be_can_write(chr);
}
}
TCPCharDriver *s = chr->opaque;
if (!s->connected)
return 0;
- s->max_size = qemu_chr_can_read(chr);
+ s->max_size = qemu_chr_be_can_write(chr);
return s->max_size;
}
if (s->do_telnetopt)
tcp_chr_process_IAC_bytes(chr, s, buf, &size);
if (size > 0)
- qemu_chr_read(chr, buf, size);
+ qemu_chr_be_write(chr, buf, size);
}
}
return qstring_from_substr((char *) d->outbuf, 0, d->outbuf_size - 1);
}
-/* NOTE: this driver can not be closed with qemu_chr_close()! */
+/* NOTE: this driver can not be closed with qemu_chr_delete()! */
void qemu_chr_close_mem(CharDriverState *chr)
{
MemoryDriver *d = chr->opaque;
#endif
};
-CharDriverState *qemu_chr_open_opts(QemuOpts *opts,
+CharDriverState *qemu_chr_new_from_opts(QemuOpts *opts,
void (*init)(struct CharDriverState *s))
{
CharDriverState *chr;
return chr;
}
-CharDriverState *qemu_chr_open(const char *label, const char *filename, void (*init)(struct CharDriverState *s))
+CharDriverState *qemu_chr_new(const char *label, const char *filename, void (*init)(struct CharDriverState *s))
{
const char *p;
CharDriverState *chr;
if (!opts)
return NULL;
- chr = qemu_chr_open_opts(opts, init);
+ chr = qemu_chr_new_from_opts(opts, init);
if (chr && qemu_opt_get_bool(opts, "mux", 0)) {
monitor_init(chr, MONITOR_USE_READLINE);
}
return chr;
}
-void qemu_chr_set_echo(struct CharDriverState *chr, bool echo)
+void qemu_chr_fe_set_echo(struct CharDriverState *chr, bool echo)
{
if (chr->chr_set_echo) {
chr->chr_set_echo(chr, echo);
}
}
-void qemu_chr_guest_open(struct CharDriverState *chr)
+void qemu_chr_fe_open(struct CharDriverState *chr)
{
if (chr->chr_guest_open) {
chr->chr_guest_open(chr);
}
}
-void qemu_chr_guest_close(struct CharDriverState *chr)
+void qemu_chr_fe_close(struct CharDriverState *chr)
{
if (chr->chr_guest_close) {
chr->chr_guest_close(chr);
}
}
-void qemu_chr_close(CharDriverState *chr)
+void qemu_chr_delete(CharDriverState *chr)
{
QTAILQ_REMOVE(&chardevs, chr, next);
if (chr->chr_close)
IOCanReadHandler *chr_can_read;
IOReadHandler *chr_read;
void *handler_opaque;
- void (*chr_send_event)(struct CharDriverState *chr, int event);
void (*chr_close)(struct CharDriverState *chr);
void (*chr_accept_input)(struct CharDriverState *chr);
void (*chr_set_echo)(struct CharDriverState *chr, bool echo);
QTAILQ_ENTRY(CharDriverState) next;
};
-QemuOpts *qemu_chr_parse_compat(const char *label, const char *filename);
-CharDriverState *qemu_chr_open_opts(QemuOpts *opts,
+/**
+ * @qemu_chr_new_from_opts:
+ *
+ * Create a new character backend from a QemuOpts list.
+ *
+ * @opts see qemu-config.c for a list of valid options
+ * @init not sure..
+ *
+ * Returns: a new character backend
+ */
+CharDriverState *qemu_chr_new_from_opts(QemuOpts *opts,
void (*init)(struct CharDriverState *s));
-CharDriverState *qemu_chr_open(const char *label, const char *filename, void (*init)(struct CharDriverState *s));
-void qemu_chr_set_echo(struct CharDriverState *chr, bool echo);
-void qemu_chr_guest_open(struct CharDriverState *chr);
-void qemu_chr_guest_close(struct CharDriverState *chr);
-void qemu_chr_close(CharDriverState *chr);
-void qemu_chr_printf(CharDriverState *s, const char *fmt, ...)
+
+/**
+ * @qemu_chr_new:
+ *
+ * Create a new character backend from a URI.
+ *
+ * @label the name of the backend
+ * @filename the URI
+ * @init not sure..
+ *
+ * Returns: a new character backend
+ */
+CharDriverState *qemu_chr_new(const char *label, const char *filename,
+ void (*init)(struct CharDriverState *s));
+
+/**
+ * @qemu_chr_delete:
+ *
+ * Destroy a character backend.
+ */
+void qemu_chr_delete(CharDriverState *chr);
+
+/**
+ * @qemu_chr_fe_set_echo:
+ *
+ * Ask the backend to override its normal echo setting. This only really
+ * applies to the stdio backend and is used by the QMP server such that you
+ * can see what you type if you try to type QMP commands.
+ *
+ * @echo true to enable echo, false to disable echo
+ */
+void qemu_chr_fe_set_echo(struct CharDriverState *chr, bool echo);
+
+/**
+ * @qemu_chr_fe_open:
+ *
+ * Open a character backend. This function call is an indication that the
+ * front end is ready to begin doing I/O.
+ */
+void qemu_chr_fe_open(struct CharDriverState *chr);
+
+/**
+ * @qemu_chr_fe_close:
+ *
+ * Close a character backend. This function call indicates that the front end
+ * no longer is able to process I/O. To process I/O again, the front end will
+ * call @qemu_chr_fe_open.
+ */
+void qemu_chr_fe_close(struct CharDriverState *chr);
+
+/**
+ * @qemu_chr_fe_printf:
+ *
+ * Write to a character backend using a printf style interface.
+ *
+ * @fmt see #printf
+ */
+void qemu_chr_fe_printf(CharDriverState *s, const char *fmt, ...)
GCC_FMT_ATTR(2, 3);
-int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
-void qemu_chr_send_event(CharDriverState *s, int event);
+
+/**
+ * @qemu_chr_fe_write:
+ *
+ * Write data to a character backend from the front end. This function will
+ * send data from the front end to the back end.
+ *
+ * @buf the data
+ * @len the number of bytes to send
+ *
+ * Returns: the number of bytes consumed
+ */
+int qemu_chr_fe_write(CharDriverState *s, const uint8_t *buf, int len);
+
+/**
+ * @qemu_chr_fe_ioctl:
+ *
+ * Issue a device specific ioctl to a backend.
+ *
+ * @cmd see CHR_IOCTL_*
+ * @arg the data associated with @cmd
+ *
+ * Returns: if @cmd is not supported by the backend, -ENOTSUP, otherwise the
+ * return value depends on the semantics of @cmd
+ */
+int qemu_chr_fe_ioctl(CharDriverState *s, int cmd, void *arg);
+
+/**
+ * @qemu_chr_fe_get_msgfd:
+ *
+ * For backends capable of fd passing, return the latest file descriptor passed
+ * by a client.
+ *
+ * Returns: -1 if fd passing isn't supported or there is no pending file
+ * descriptor. If a file descriptor is returned, subsequent calls to
+ * this function will return -1 until a client sends a new file
+ * descriptor.
+ */
+int qemu_chr_fe_get_msgfd(CharDriverState *s);
+
+/**
+ * @qemu_chr_be_can_write:
+ *
+ * Determine how much data the front end can currently accept. This function
+ * returns the number of bytes the front end can accept. If it returns 0, the
+ * front end cannot receive data at the moment. The function must be polled
+ * to determine when data can be received.
+ *
+ * Returns: the number of bytes the front end can receive via @qemu_chr_be_write
+ */
+int qemu_chr_be_can_write(CharDriverState *s);
+
+/**
+ * @qemu_chr_be_write:
+ *
+ * Write data from the back end to the front end. Before issuing this call,
+ * the caller should call @qemu_chr_be_can_write to determine how much data
+ * the front end can currently accept.
+ *
+ * @buf a buffer to receive data from the front end
+ * @len the number of bytes to receive from the front end
+ */
+void qemu_chr_be_write(CharDriverState *s, uint8_t *buf, int len);
+
void qemu_chr_add_handlers(CharDriverState *s,
IOCanReadHandler *fd_can_read,
IOReadHandler *fd_read,
IOEventHandler *fd_event,
void *opaque);
-int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
+
void qemu_chr_generic_open(CharDriverState *s);
-int qemu_chr_can_read(CharDriverState *s);
-void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
-int qemu_chr_get_msgfd(CharDriverState *s);
void qemu_chr_accept_input(CharDriverState *s);
int qemu_chr_add_client(CharDriverState *s, int fd);
void qemu_chr_info_print(Monitor *mon, const QObject *ret_data);
void qemu_chr_info(Monitor *mon, QObject **ret_data);
CharDriverState *qemu_chr_find(const char *name);
+QemuOpts *qemu_chr_parse_compat(const char *label, const char *filename);
+
/* add an eventfd to the qemu devices that are polled */
CharDriverState *qemu_chr_open_eventfd(int eventfd);
@echo "missing libtool. please install and rerun configure"; exit 1
else
%.lo: %.c
- $(call quiet-command,libtool --mode=compile --quiet --tag=CC $(CC) $(QEMU_INCLUDES) $(QEMU_CFLAGS) $(QEMU_DGFLAGS) $(CFLAGS) -c -o $@ $<," lt CC $@")
+ $(call quiet-command,$(LIBTOOL) --mode=compile --quiet --tag=CC $(CC) $(QEMU_INCLUDES) $(QEMU_CFLAGS) $(QEMU_DGFLAGS) $(CFLAGS) -c -o $@ $<," lt CC $@")
endif
%.o: %.S
ssize_t slirp_send(struct socket *so, const void *buf, size_t len, int flags)
{
if (so->s == -1 && so->extra) {
- qemu_chr_write(so->extra, buf, len);
+ qemu_chr_fe_write(so->extra, buf, len);
return len;
}
while (len > 0) {
last_out = MIN(len, VMC_MAX_HOST_WRITE);
- if (qemu_chr_can_read(scd->chr) < last_out) {
+ if (qemu_chr_be_can_write(scd->chr) < last_out) {
break;
}
- qemu_chr_read(scd->chr, p, last_out);
+ qemu_chr_be_write(scd->chr, p, last_out);
out += last_out;
len -= last_out;
p += last_out;
void qemu_announce_self(void);
-void main_loop_wait(int nonblocking);
+int main_loop_wait(int nonblocking);
bool qemu_savevm_state_blocked(Monitor *mon);
int qemu_savevm_state_begin(Monitor *mon, QEMUFile *f, int blk_enable,
#endif
/* Exception state register bits definition */
-#define ESR_ST 23 /* Exception was caused by a store type access. */
+#define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
+#define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
+#define ESR_PTR (1 << (63 - 38)) /* Trap */
+#define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
+#define ESR_ST (1 << (63 - 40)) /* Store Operation */
+#define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
+#define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
+#define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
+#define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
+#define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
+#define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
+#define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
+#define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
+#define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
+#define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
+#define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
enum {
POWERPC_FLAG_NONE = 0x00000000,
env->exception_index = POWERPC_EXCP_DTLB;
env->error_code = 0;
env->spr[SPR_BOOKE_DEAR] = address;
- env->spr[SPR_BOOKE_ESR] = rw ? 1 << ESR_ST : 0;
+ env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0;
return -1;
case POWERPC_MMU_REAL:
cpu_abort(env, "PowerPC in real mode should never raise "
} else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
(env->mmu_model == POWERPC_MMU_BOOKE206)) {
env->spr[SPR_BOOKE_DEAR] = address;
- env->spr[SPR_BOOKE_ESR] = rw ? 1 << ESR_ST : 0;
+ env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0;
} else {
env->spr[SPR_DAR] = address;
if (rw == 1) {
if (lpes1 == 0)
new_msr |= (target_ulong)MSR_HVB;
msr |= 0x00080000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PIL;
break;
case POWERPC_EXCP_PRIV:
if (lpes1 == 0)
new_msr |= (target_ulong)MSR_HVB;
msr |= 0x00040000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PPR;
break;
case POWERPC_EXCP_TRAP:
if (lpes1 == 0)
new_msr |= (target_ulong)MSR_HVB;
msr |= 0x00020000;
+ env->spr[SPR_BOOKE_ESR] = ESR_PTR;
break;
default:
/* Should never occur */
cpu_abort(env, "Debug exception is not implemented yet !\n");
goto store_next;
case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */
+ env->spr[SPR_BOOKE_ESR] = ESR_SPV;
goto store_current;
case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
/* XXX: TODO */
cpu_abort(env, "Embedded floating point data exception "
"is not implemented yet !\n");
+ env->spr[SPR_BOOKE_ESR] = ESR_SPV;
goto store_next;
case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
/* XXX: TODO */
cpu_abort(env, "Embedded floating point round exception "
"is not implemented yet !\n");
+ env->spr[SPR_BOOKE_ESR] = ESR_SPV;
goto store_next;
case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
/* XXX: TODO */
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
TCGv_i32 t0 = tcg_temp_local_new_i32(); \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
TCGv_i32 t0 = tcg_temp_local_new_i32(); \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
TCGv_i32 t0 = tcg_temp_local_new_i32(); \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
static inline void gen_evmergehi(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
TCGv_i32 t0 = tcg_temp_local_new_i32(); \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
int l1 = gen_new_label(); \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
int l1 = gen_new_label(); \
static inline void gen_evmergelo(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
static inline void gen_evmergehilo(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
static inline void gen_evmergelohi(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
TCGv_i64 t0, t1;
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
TCGv_i64 tmp;
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
TCGv_i64 tmp;
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
TCGv_i64 t0, t1;
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
{ \
TCGv t0; \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
gen_set_access_type(ctx, ACCESS_INT); \
TCGv_i32 t0, t1; \
TCGv_i64 t2; \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
t0 = tcg_temp_new_i32(); \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
{ \
TCGv_i32 t0, t1; \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
t0 = tcg_temp_new_i32(); \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
{ \
TCGv_i64 t0, t1; \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
t0 = tcg_temp_new_i64(); \
static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
{ \
TCGv_i64 t0, t1; \
if (unlikely(!ctx->spe_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_APU); \
+ gen_exception(ctx, POWERPC_EXCP_SPEU); \
return; \
} \
t0 = tcg_temp_new_i64(); \
static inline void gen_evfsabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
static inline void gen_evfsnabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
static inline void gen_evfsneg(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
static inline void gen_efsabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
static inline void gen_efsnabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
static inline void gen_efsneg(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
static inline void gen_efdabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
static inline void gen_efdnabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
static inline void gen_efdneg(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_APU);
+ gen_exception(ctx, POWERPC_EXCP_SPEU);
return;
}
#if defined(TARGET_PPC64)
}
break;
+ case INDEX_op_deposit_i32:
+ tcg_out32 (s, RLWIMI
+ | RA (args[0])
+ | RS (args[2])
+ | SH (args[3])
+ | MB (32 - args[3] - args[4])
+ | ME (31 - args[3])
+ );
+ break;
+
default:
tcg_dump_ops (s, stderr);
tcg_abort ();
{ INDEX_op_ext16s_i32, { "r", "r" } },
{ INDEX_op_ext16u_i32, { "r", "r" } },
+ { INDEX_op_deposit_i32, { "r", "0", "r" } },
+
{ -1 },
};
#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 1
#define TCG_TARGET_HAS_nor_i32 1
-#define TCG_TARGET_HAS_deposit_i32 0
+#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_AREG0 TCG_REG_R27
#define SRAWI XO31(824)
#define NEG XO31(104)
#define MFCR XO31( 19)
+#define NOR XO31(124)
#define CNTLZW XO31( 26)
#define CNTLZD XO31( 58)
tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
break;
+ case INDEX_op_not_i32:
+ case INDEX_op_not_i64:
+ tcg_out32 (s, NOR | SAB (args[1], args[0], args[1]));
+ break;
+
case INDEX_op_add_i64:
if (const_args[2])
ppc_addi64 (s, args[0], args[1], args[2]);
tcg_out32 (s, c | RS (args[1]) | RA (args[0]));
break;
+ case INDEX_op_ext32u_i64:
+ tcg_out_rld (s, RLDICR, args[0], args[1], 0, 32);
+ break;
+
case INDEX_op_setcond_i32:
tcg_out_setcond (s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
const_args[2]);
{ INDEX_op_brcond_i64, { "r", "ri" } },
{ INDEX_op_neg_i32, { "r", "r" } },
+ { INDEX_op_not_i32, { "r", "r" } },
{ INDEX_op_add_i64, { "r", "r", "ri" } },
{ INDEX_op_sub_i64, { "r", "r", "ri" } },
{ INDEX_op_remu_i64, { "r", "r", "r" } },
{ INDEX_op_neg_i64, { "r", "r" } },
+ { INDEX_op_not_i64, { "r", "r" } },
{ INDEX_op_qemu_ld8u, { "r", "L" } },
{ INDEX_op_qemu_ld8s, { "r", "L" } },
{ INDEX_op_ext8s_i64, { "r", "r" } },
{ INDEX_op_ext16s_i64, { "r", "r" } },
{ INDEX_op_ext32s_i64, { "r", "r" } },
+ { INDEX_op_ext32u_i64, { "r", "r" } },
{ INDEX_op_setcond_i32, { "r", "r", "ri" } },
{ INDEX_op_setcond_i64, { "r", "r", "ri" } },
#define TCG_TARGET_HAS_ext16u_i32 0
#define TCG_TARGET_HAS_bswap16_i32 0
#define TCG_TARGET_HAS_bswap32_i32 0
-#define TCG_TARGET_HAS_not_i32 0
+#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_neg_i32 1
#define TCG_TARGET_HAS_andc_i32 0
#define TCG_TARGET_HAS_orc_i32 0
#define TCG_TARGET_HAS_ext32s_i64 1
#define TCG_TARGET_HAS_ext8u_i64 0
#define TCG_TARGET_HAS_ext16u_i64 0
-#define TCG_TARGET_HAS_ext32u_i64 0
+#define TCG_TARGET_HAS_ext32u_i64 1
#define TCG_TARGET_HAS_bswap16_i64 0
#define TCG_TARGET_HAS_bswap32_i64 0
#define TCG_TARGET_HAS_bswap64_i64 0
-#define TCG_TARGET_HAS_not_i64 0
+#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_neg_i64 1
#define TCG_TARGET_HAS_andc_i64 0
#define TCG_TARGET_HAS_orc_i64 0
#if defined(CONFIG_DEBUG_TCG)
i = 0;
for (op = 0; op < ARRAY_SIZE(tcg_op_defs); op++) {
- if (op < INDEX_op_call || op == INDEX_op_debug_insn_start) {
+ const TCGOpDef *def = &tcg_op_defs[op];
+ if (op < INDEX_op_call
+ || op == INDEX_op_debug_insn_start
+ || (def->flags & TCG_OPF_NOT_PRESENT)) {
/* Wrong entry in op definitions? */
- if (tcg_op_defs[op].used) {
- fprintf(stderr, "Invalid op definition for %s\n",
- tcg_op_defs[op].name);
+ if (def->used) {
+ fprintf(stderr, "Invalid op definition for %s\n", def->name);
i = 1;
}
} else {
/* Missing entry in op definitions? */
- if (!tcg_op_defs[op].used) {
- fprintf(stderr, "Missing op definition for %s\n",
- tcg_op_defs[op].name);
+ if (!def->used) {
+ fprintf(stderr, "Missing op definition for %s\n", def->name);
i = 1;
}
}
# hw/apic.c
disable apic_local_deliver(int vector, uint32_t lvt) "vector %d delivery mode %d"
-disable apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t polarity, uint8_t trigger_mode) "dest %d dest_mode %d delivery_mode %d vector %d polarity %d trigger_mode %d"
+disable apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t trigger_mode) "dest %d dest_mode %d delivery_mode %d vector %d trigger_mode %d"
disable cpu_set_apic_base(uint64_t val) "%016"PRIx64""
disable cpu_get_apic_base(uint64_t val) "%016"PRIx64""
disable apic_mem_readl(uint64_t addr, uint32_t val) "%"PRIx64" = %08x"
absolute_enabled = 1;
}
} else if (absolute_enabled) {
- sdl_grab_end();
+ if (!gui_fullscreen) {
+ sdl_grab_end();
+ }
absolute_enabled = 0;
}
}
{
USBRedirDevice *dev = priv;
- return qemu_chr_write(dev->cs, data, count);
+ return qemu_chr_fe_write(dev->cs, data, count);
}
/*
{
USBRedirDevice *dev = DO_UPCAST(USBRedirDevice, dev, udev);
- qemu_chr_close(dev->cs);
+ qemu_chr_delete(dev->cs);
/* Note must be done after qemu_chr_close, as that causes a close event */
qemu_bh_delete(dev->open_close_bh);
qemu_notify_event();
}
-void main_loop_wait(int nonblocking)
+int main_loop_wait(int nonblocking)
{
fd_set rfds, wfds, xfds;
int ret, nfds;
qemu_iohandler_fill(&nfds, &rfds, &wfds, &xfds);
slirp_select_fill(&nfds, &rfds, &wfds, &xfds);
- qemu_mutex_unlock_iothread();
+ if (timeout > 0) {
+ qemu_mutex_unlock_iothread();
+ }
+
ret = select(nfds + 1, &rfds, &wfds, &xfds, &tv);
- qemu_mutex_lock_iothread();
+
+ if (timeout > 0) {
+ qemu_mutex_lock_iothread();
+ }
qemu_iohandler_poll(&rfds, &wfds, &xfds, ret);
slirp_select_poll(&rfds, &wfds, &xfds, (ret < 0));
them. */
qemu_bh_poll();
+ return ret;
}
#ifndef CONFIG_IOTHREAD
static void main_loop(void)
{
- bool nonblocking = false;
+ bool nonblocking;
+ int last_io __attribute__ ((unused)) = 0;
#ifdef CONFIG_PROFILER
int64_t ti;
#endif
qemu_main_loop_start();
for (;;) {
-#ifndef CONFIG_IOTHREAD
+#ifdef CONFIG_IOTHREAD
+ nonblocking = !kvm_enabled() && last_io > 0;
+#else
nonblocking = cpu_exec_all();
if (vm_request_pending()) {
nonblocking = true;
#ifdef CONFIG_PROFILER
ti = profile_getclock();
#endif
- main_loop_wait(nonblocking);
+ last_io = main_loop_wait(nonblocking);
#ifdef CONFIG_PROFILER
dev_time += profile_getclock() - ti;
#endif
{
CharDriverState *chr;
- chr = qemu_chr_open_opts(opts, NULL);
+ chr = qemu_chr_new_from_opts(opts, NULL);
if (!chr)
return -1;
return 0;
exit(1);
}
snprintf(label, sizeof(label), "serial%d", index);
- serial_hds[index] = qemu_chr_open(label, devname, NULL);
+ serial_hds[index] = qemu_chr_new(label, devname, NULL);
if (!serial_hds[index]) {
fprintf(stderr, "qemu: could not open serial device '%s': %s\n",
devname, strerror(errno));
exit(1);
}
snprintf(label, sizeof(label), "parallel%d", index);
- parallel_hds[index] = qemu_chr_open(label, devname, NULL);
+ parallel_hds[index] = qemu_chr_new(label, devname, NULL);
if (!parallel_hds[index]) {
fprintf(stderr, "qemu: could not open parallel device '%s': %s\n",
devname, strerror(errno));
qemu_opt_set(dev_opts, "driver", "virtconsole");
snprintf(label, sizeof(label), "virtcon%d", index);
- virtcon_hds[index] = qemu_chr_open(label, devname, NULL);
+ virtcon_hds[index] = qemu_chr_new(label, devname, NULL);
if (!virtcon_hds[index]) {
fprintf(stderr, "qemu: could not open virtio console '%s': %s\n",
devname, strerror(errno));
{
QemuOpts *opts;
- if (!qemu_chr_open("debugcon", devname, NULL)) {
+ if (!qemu_chr_new("debugcon", devname, NULL)) {
exit(1);
}
opts = qemu_opts_create(qemu_find_opts("device"), "debugcon", 1);
projects / mirror_qemu.git / commitdiff