drm/amdgpu: move vm definitions into amdgpu_vm header

Demangle amdgpu.h.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 64f9ad4056daf47fd448dcad1015d48f9a8edda1..ef4fb6a6f9db38c9e1679190bb09f226f73cc390 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -257,27 +257,6 @@ amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
                               const struct amdgpu_ip_block_version *ip_block_version);
 
-/* provided by hw blocks that can write ptes, e.g., sdma */
-struct amdgpu_vm_pte_funcs {
-       /* number of dw to reserve per operation */
-       unsigned        copy_pte_num_dw;
-
-       /* copy pte entries from GART */
-       void (*copy_pte)(struct amdgpu_ib *ib,
-                        uint64_t pe, uint64_t src,
-                        unsigned count);
-
-       /* write pte one entry at a time with addr mapping */
-       void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
-                         uint64_t value, unsigned count,
-                         uint32_t incr);
-       /* for linear pte/pde updates without addr mapping */
-       void (*set_pte_pde)(struct amdgpu_ib *ib,
-                           uint64_t pe,
-                           uint64_t addr, unsigned count,
-                           uint32_t incr, uint64_t flags);
-};
-
 /*
  * BIOS.
  */
@@ -1249,9 +1228,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
-#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
-#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
-#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
 
 /* Common functions */
 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 67a15d439ac006f97b48ffe7e74544d6688bf452..ffda53420f8c1a68e1478054393562a457ee6ae0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -160,6 +160,27 @@ struct amdgpu_vm_pt {
        struct amdgpu_vm_pt             *entries;
 };
 
+/* provided by hw blocks that can write ptes, e.g., sdma */
+struct amdgpu_vm_pte_funcs {
+       /* number of dw to reserve per operation */
+       unsigned        copy_pte_num_dw;
+
+       /* copy pte entries from GART */
+       void (*copy_pte)(struct amdgpu_ib *ib,
+                        uint64_t pe, uint64_t src,
+                        unsigned count);
+
+       /* write pte one entry at a time with addr mapping */
+       void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
+                         uint64_t value, unsigned count,
+                         uint32_t incr);
+       /* for linear pte/pde updates without addr mapping */
+       void (*set_pte_pde)(struct amdgpu_ib *ib,
+                           uint64_t pe,
+                           uint64_t addr, unsigned count,
+                           uint32_t incr, uint64_t flags);
+};
+
 #define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr))
 #define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48)
 #define AMDGPU_VM_FAULT_ADDR(fault)  ((u64)(fault) & 0xfffffffff000ULL)
@@ -266,6 +287,10 @@ struct amdgpu_vm_manager {
        spinlock_t                              pasid_lock;
 };
 
+#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
+#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
+#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
+
 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,