octeontx2-af: Misc cleanups in cgx driver

* Do CGX init before NIX init
  This would add consistency in NIX code that depends on cgx ports

* Few other misc cleanups
  - rvu_cgx_probe renamed as rvu_cgx_init for consistency
  - rvu_cgx_exit wrapper added to take care of the exit path
  - Added error check on cgx_lmac_event_handler_init
  - Minor cleanups in cgx.h related to tab alignment
  - Removed redundant ids from enum cgx_cmd_id

Signed-off-by: Linu Cherian <lcherian@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h
index 3bd38ed6d68bd6652884b8298c6d645fd6c8f815..8d7d77b3035c63ce1205f30e365c53e9dd1b61b0 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h
@@ -27,34 +27,34 @@
 
 /* Registers */
 #define CGXX_CMRX_CFG                  0x00
-#define  CMR_EN                                        BIT_ULL(55)
-#define  DATA_PKT_TX_EN                                BIT_ULL(53)
-#define  DATA_PKT_RX_EN                                BIT_ULL(54)
-#define  CGX_LMAC_TYPE_SHIFT                   40
-#define  CGX_LMAC_TYPE_MASK                    0xF
+#define CMR_EN                         BIT_ULL(55)
+#define DATA_PKT_TX_EN                 BIT_ULL(53)
+#define DATA_PKT_RX_EN                 BIT_ULL(54)
+#define CGX_LMAC_TYPE_SHIFT            40
+#define CGX_LMAC_TYPE_MASK             0xF
 #define CGXX_CMRX_INT                  0x040
-#define  FW_CGX_INT                            BIT_ULL(1)
+#define FW_CGX_INT                     BIT_ULL(1)
 #define CGXX_CMRX_INT_ENA_W1S          0x058
 #define CGXX_CMRX_RX_ID_MAP            0x060
 #define CGXX_CMRX_RX_STAT0             0x070
 #define CGXX_CMRX_RX_LMACS             0x128
 #define CGXX_CMRX_RX_DMAC_CTL0         0x1F8
-#define  CGX_DMAC_CTL0_CAM_ENABLE              BIT_ULL(3)
-#define  CGX_DMAC_CAM_ACCEPT                   BIT_ULL(3)
-#define  CGX_DMAC_MCAST_MODE                   BIT_ULL(1)
-#define  CGX_DMAC_BCAST_MODE                   BIT_ULL(0)
+#define CGX_DMAC_CTL0_CAM_ENABLE       BIT_ULL(3)
+#define CGX_DMAC_CAM_ACCEPT            BIT_ULL(3)
+#define CGX_DMAC_MCAST_MODE            BIT_ULL(1)
+#define CGX_DMAC_BCAST_MODE            BIT_ULL(0)
 #define CGXX_CMRX_RX_DMAC_CAM0         0x200
-#define  CGX_DMAC_CAM_ADDR_ENABLE              BIT_ULL(48)
+#define CGX_DMAC_CAM_ADDR_ENABLE       BIT_ULL(48)
 #define CGXX_CMRX_RX_DMAC_CAM1         0x400
-#define CGX_RX_DMAC_ADR_MASK                   GENMASK_ULL(47, 0)
+#define CGX_RX_DMAC_ADR_MASK           GENMASK_ULL(47, 0)
 #define CGXX_CMRX_TX_STAT0             0x700
 #define CGXX_SCRATCH0_REG              0x1050
 #define CGXX_SCRATCH1_REG              0x1058
 #define CGX_CONST                      0x2000
 #define CGXX_SPUX_CONTROL1             0x10000
-#define  CGXX_SPUX_CONTROL1_LBK                        BIT_ULL(14)
+#define CGXX_SPUX_CONTROL1_LBK         BIT_ULL(14)
 #define CGXX_GMP_PCS_MRX_CTL           0x30000
-#define  CGXX_GMP_PCS_MRX_CTL_LBK              BIT_ULL(14)
+#define CGXX_GMP_PCS_MRX_CTL_LBK       BIT_ULL(14)
 
 #define CGX_COMMAND_REG                        CGXX_SCRATCH1_REG
 #define CGX_EVENT_REG                  CGXX_SCRATCH0_REG

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h
index fa17af3f4ba7ef8219006c58e9c189336556e003..2d9fe51c66166efb22a612d0f09d8c9a3c25e23a 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h
@@ -78,8 +78,6 @@ enum cgx_cmd_id {
        CGX_CMD_LINK_STATE_CHANGE,
        CGX_CMD_MODE_CHANGE,            /* hot plug support */
        CGX_CMD_INTF_SHUTDOWN,
-       CGX_CMD_IRQ_ENABLE,
-       CGX_CMD_IRQ_DISABLE,
 };
 
 /* async event ids */

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
index 40eb3ad725f5ff3be1546a029bfbb7bb01ae3972..4d061d9719561017ac05afaa2dd397fdd93282b6 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
@@ -811,17 +811,26 @@ init:
 
        err = rvu_npc_init(rvu);
        if (err)
-               return err;
+               goto exit;
+
+       err = rvu_cgx_init(rvu);
+       if (err)
+               goto exit;
 
        err = rvu_npa_init(rvu);
        if (err)
-               return err;
+               goto cgx_err;
 
        err = rvu_nix_init(rvu);
        if (err)
-               return err;
+               goto cgx_err;
 
        return 0;
+
+cgx_err:
+       rvu_cgx_exit(rvu);
+exit:
+       return err;
 }
 
 /* NPA and NIX admin queue APIs */
@@ -2419,13 +2428,9 @@ static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
        if (err)
                goto err_hwsetup;
 
-       err = rvu_cgx_probe(rvu);
-       if (err)
-               goto err_mbox;
-
        err = rvu_flr_init(rvu);
        if (err)
-               goto err_cgx;
+               goto err_mbox;
 
        err = rvu_register_interrupts(rvu);
        if (err)
@@ -2441,11 +2446,10 @@ err_irq:
        rvu_unregister_interrupts(rvu);
 err_flr:
        rvu_flr_wq_destroy(rvu);
-err_cgx:
-       rvu_cgx_wq_destroy(rvu);
 err_mbox:
        rvu_mbox_destroy(&rvu->afpf_wq_info);
 err_hwsetup:
+       rvu_cgx_exit(rvu);
        rvu_reset_all_blocks(rvu);
        rvu_free_hw_resources(rvu);
 err_release_regions:
@@ -2465,7 +2469,7 @@ static void rvu_remove(struct pci_dev *pdev)
 
        rvu_unregister_interrupts(rvu);
        rvu_flr_wq_destroy(rvu);
-       rvu_cgx_wq_destroy(rvu);
+       rvu_cgx_exit(rvu);
        rvu_mbox_destroy(&rvu->afpf_wq_info);
        rvu_disable_sriov(rvu);
        rvu_reset_all_blocks(rvu);

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index c8409bc5d9c38b296bd21f00b87a73bb70a53486..96049e275335af90d69637b312b0e576219c5614 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -316,8 +316,8 @@ static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)
        *lmac_id = (map & 0xF);
 }
 
-int rvu_cgx_probe(struct rvu *rvu);
-void rvu_cgx_wq_destroy(struct rvu *rvu);
+int rvu_cgx_init(struct rvu *rvu);
+int rvu_cgx_exit(struct rvu *rvu);
 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu);
 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start);
 int rvu_mbox_handler_cgx_start_rxtx(struct rvu *rvu, struct msg_req *req,

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
index 1de6eb528d08d3b3fa4daf05432b699c2b20de51..1f1bc837bcd6a7c2b1098459e75f6b47a0174767 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
@@ -216,7 +216,7 @@ static void cgx_evhandler_task(struct work_struct *work)
        } while (1);
 }
 
-static void cgx_lmac_event_handler_init(struct rvu *rvu)
+static int cgx_lmac_event_handler_init(struct rvu *rvu)
 {
        struct cgx_event_cb cb;
        int cgx, lmac, err;
@@ -228,7 +228,7 @@ static void cgx_lmac_event_handler_init(struct rvu *rvu)
        rvu->cgx_evh_wq = alloc_workqueue("rvu_evh_wq", 0, 0);
        if (!rvu->cgx_evh_wq) {
                dev_err(rvu->dev, "alloc workqueue failed");
-               return;
+               return -ENOMEM;
        }
 
        cb.notify_link_chg = cgx_lmac_postevent; /* link change call back */
@@ -244,9 +244,11 @@ static void cgx_lmac_event_handler_init(struct rvu *rvu)
                                        cgx, lmac);
                }
        }
+
+       return 0;
 }
 
-void rvu_cgx_wq_destroy(struct rvu *rvu)
+static void rvu_cgx_wq_destroy(struct rvu *rvu)
 {
        if (rvu->cgx_evh_wq) {
                flush_workqueue(rvu->cgx_evh_wq);
@@ -255,9 +257,9 @@ void rvu_cgx_wq_destroy(struct rvu *rvu)
        }
 }
 
-int rvu_cgx_probe(struct rvu *rvu)
+int rvu_cgx_init(struct rvu *rvu)
 {
-       int i, err;
+       int cgx, err;
 
        /* find available cgx ports */
        rvu->cgx_cnt = cgx_get_cgx_cnt();
@@ -272,8 +274,8 @@ int rvu_cgx_probe(struct rvu *rvu)
                return -ENOMEM;
 
        /* Initialize the cgxdata table */
-       for (i = 0; i < rvu->cgx_cnt; i++)
-               rvu->cgx_idmap[i] = cgx_get_pdata(i);
+       for (cgx = 0; cgx < rvu->cgx_cnt; cgx++)
+               rvu->cgx_idmap[cgx] = cgx_get_pdata(cgx);
 
        /* Map CGX LMAC interfaces to RVU PFs */
        err = rvu_map_cgx_lmac_pf(rvu);
@@ -281,7 +283,16 @@ int rvu_cgx_probe(struct rvu *rvu)
                return err;
 
        /* Register for CGX events */
-       cgx_lmac_event_handler_init(rvu);
+       err = cgx_lmac_event_handler_init(rvu);
+       if (err)
+               return err;
+
+       return 0;
+}
+
+int rvu_cgx_exit(struct rvu *rvu)
+{
+       rvu_cgx_wq_destroy(rvu);
        return 0;
 }