#define GPC_CLK_MAX 6
+#define PGC_DOMAIN_FLAG_NO_PD BIT(0)
+
struct imx_pm_domain {
struct generic_pm_domain base;
struct regmap *regmap;
unsigned int reg_offs;
signed char cntr_pdn_bit;
unsigned int ipg_rate_mhz;
+ unsigned int flags;
};
static inline struct imx_pm_domain *
int iso, iso2sw;
u32 val;
+ if (pd->flags & PGC_DOMAIN_FLAG_NO_PD)
+ return -EBUSY;
+
/* Read ISO and ISO2SW power down delays */
regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val);
iso = val & 0x3f;
struct imx_gpc_dt_data {
int num_domains;
+ bool err009619_present;
};
static const struct imx_gpc_dt_data imx6q_dt_data = {
.num_domains = 2,
+ .err009619_present = false,
+};
+
+static const struct imx_gpc_dt_data imx6qp_dt_data = {
+ .num_domains = 2,
+ .err009619_present = true,
};
static const struct imx_gpc_dt_data imx6sl_dt_data = {
.num_domains = 3,
+ .err009619_present = false,
};
static const struct of_device_id imx_gpc_dt_ids[] = {
{ .compatible = "fsl,imx6q-gpc", .data = &imx6q_dt_data },
+ { .compatible = "fsl,imx6qp-gpc", .data = &imx6qp_dt_data },
{ .compatible = "fsl,imx6sl-gpc", .data = &imx6sl_dt_data },
{ }
};
return ret;
}
+ /* Disable PU power down in normal operation if ERR009619 is present */
+ if (of_id_data->err009619_present)
+ imx_gpc_domains[GPC_PGC_DOMAIN_PU].flags |=
+ PGC_DOMAIN_FLAG_NO_PD;
+
if (!pgc_node) {
ret = imx_gpc_old_dt_init(&pdev->dev, regmap,
of_id_data->num_domains);