tty/serial: Add explicit PORT_TEGRA type

Tegra's UART is currently auto-detected as PORT_XSCALE due to register
bit UART_IER.UUE being writable. However, the Tegra documentation states
that this register bit is reserved. Hence, we should not program it.

Instead, the documentation specifies that the UART is 16550 compatible.
However, Tegra does need register bit UART_IER.RTOIE set, which is not
enabled by any 16550 port type. This was not noticed before, since
PORT_XSCALE enables CAP_UUE, which conflates both UUE and RTOIE bit
programming.

This change defines PORT_TEGRA that doesn't set UART_CAP_UUE, but does
set UART_CAP_RTOIE, which is a new capability indicating that the RTOIE
bit needs to be enabled.

Based-on-code-by: Laxman Dewangan <ldewangan@nvidia.com>
Cc: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

diff --git a/drivers/tty/serial/8250.c b/drivers/tty/serial/8250.c
index 54482d724fee67c4b531fb42ebcf5f8ec0aede26..a5e290de8c935cd31561dd98b5d6c37179331a05 100644 (file)
--- a/drivers/tty/serial/8250.c
+++ b/drivers/tty/serial/8250.c
@@ -271,7 +271,7 @@ static const struct serial8250_config uart_config[] = {
                .fifo_size      = 32,
                .tx_loadsz      = 32,
                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
-               .flags          = UART_CAP_FIFO | UART_CAP_UUE,
+               .flags          = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
        },
        [PORT_RM9000] = {
                .name           = "RM9000",
@@ -301,6 +301,14 @@ static const struct serial8250_config uart_config[] = {
                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
                .flags          = UART_CAP_FIFO | UART_CAP_AFE,
        },
+       [PORT_TEGRA] = {
+               .name           = "Tegra",
+               .fifo_size      = 32,
+               .tx_loadsz      = 8,
+               .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
+                                 UART_FCR_T_TRIG_01,
+               .flags          = UART_CAP_FIFO | UART_CAP_RTOIE,
+       },
 };
 
 #if defined(CONFIG_MIPS_ALCHEMY)
@@ -2403,7 +2411,9 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
                        UART_ENABLE_MS(&up->port, termios->c_cflag))
                up->ier |= UART_IER_MSI;
        if (up->capabilities & UART_CAP_UUE)
-               up->ier |= UART_IER_UUE | UART_IER_RTOIE;
+               up->ier |= UART_IER_UUE;
+       if (up->capabilities & UART_CAP_RTOIE)
+               up->ier |= UART_IER_RTOIE;
 
        serial_out(up, UART_IER, up->ier);
 

diff --git a/drivers/tty/serial/8250.h b/drivers/tty/serial/8250.h
index d13b586c0f725994abcf3eb699c319072a62a941..6edf4a6a22d4b538e188d5e615634d4a0a7a6edc 100644 (file)
--- a/drivers/tty/serial/8250.h
+++ b/drivers/tty/serial/8250.h
@@ -42,6 +42,7 @@ struct serial8250_config {
 #define UART_CAP_SLEEP (1 << 10)       /* UART has IER sleep */
 #define UART_CAP_AFE   (1 << 11)       /* MCR-based hw flow control */
 #define UART_CAP_UUE   (1 << 12)       /* UART needs IER bit 6 set (Xscale) */
+#define UART_CAP_RTOIE (1 << 13)       /* UART needs IER bit 4 set (Xscale, Tegra) */
 
 #define UART_BUG_QUOT  (1 << 0)        /* UART has buggy quot LSB */
 #define UART_BUG_TXEN  (1 << 1)        /* UART has buggy TX IIR status */

diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 95d479ba514e4d5d2a354e889a05d44a757a2e3f..a5c31146a337dff33441ec6f61f3af92861f6a8e 100644 (file)
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -45,7 +45,8 @@
 #define PORT_OCTEON    17      /* Cavium OCTEON internal UART */
 #define PORT_AR7       18      /* Texas Instruments AR7 internal UART */
 #define PORT_U6_16550A 19      /* ST-Ericsson U6xxx internal UART */
-#define PORT_MAX_8250  19      /* max port ID */
+#define PORT_TEGRA     20      /* NVIDIA Tegra internal UART */
+#define PORT_MAX_8250  20      /* max port ID */
 
 /*
  * ARM specific type numbers.  These are not currently guaranteed

diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h
index 3ecb71a9e505901c1a0ff3a3780ba29d3c4c3741..5f66e8499fb968af75b637ebaa4c0ad9f84e47e2 100644 (file)
--- a/include/linux/serial_reg.h
+++ b/include/linux/serial_reg.h
@@ -57,6 +57,7 @@
  * ST16C654:    8  16  56  60           8  16  32  56  PORT_16654
  * TI16C750:    1  16  32  56          xx  xx  xx  xx  PORT_16750
  * TI16C752:    8  16  56  60           8  16  32  56
+ * Tegra:       1   4   8  14          16   8   4   1  PORT_TEGRA
  */
 #define UART_FCR_R_TRIG_00     0x00
 #define UART_FCR_R_TRIG_01     0x40