drm/i915: Make display workaround upper bounds exclusive

Workarounds are documented in the bspec with an exclusive upper bound
(i.e., a "fixed" stepping that no longer needs the workaround).  This
makes our driver's use of an inclusive upper bound for stepping ranges
confusing; the differing notation between code and bspec makes it very
easy for mistakes to creep in.

Let's switch the upper bound of our IS_{GT,DISP}_STEP macros over to use
an exclusive upper bound like the bspec does.  This also has the benefit
of helping make sure workarounds are properly handled for new minor
steppings that show up (e.g., an A1 between the A0 and B0 we already
knew about) --- if the new intermediate stepping pulls in hardware fixes
early, there will be an update to the workaround definition which lets
us know we need to change our code.  If the new stepping does not pull a
hardware fix earlier, then the new stepping will already be captured
properly by the "[begin, fix)" range in the code.

We'll probably need to be extra vigilant in code review of new
workarounds for the near future to make sure developers notice the new
semantics of workaround bounds.  But we just migrated a bunch of our
platforms from the IS_REVID bounds over to IS_{GT,DISP}_STEP, so people
are already adjusting to the new macros and now is a good time to make
this change too.

[mattrope: Split out display changes to apply through intel-next tree]
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210717051426.4120328-8-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 71067a62264dede88d1fb6abb269076f7d8997d9..944fb13b9d98baa3e08ac26dca7e8d5b846a6d80 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2879,7 +2879,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
                dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
                dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
                /* Wa_22011320316:adl-p[a0] */
-               if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+               if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
                        dev_priv->cdclk.table = adlp_a_step_cdclk_table;
                else
                        dev_priv->cdclk.table = adlp_cdclk_table;

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index e3aaf9678b07e2a400f8693eea7f2be1c4e5d4f2..bec380e58f4063168fd02093fc0c1e97cff74ca7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5799,10 +5799,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
        int config, i;
 
        if (IS_ALDERLAKE_S(dev_priv) ||
-           IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
-           IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
-           IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
-               /* Wa_1409767108:tgl,rkl,dg1,adl-s */
+           IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+           IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+           IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
+               /* Wa_1409767108:tgl,dg1,adl-s */
                table = wa_1409767108_buddy_page_masks;
        else
                table = tgl_buddy_page_masks;

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 13d31247d2f3b52c9fd364aa25d263e394a0095a..a54e71e4e568c5cea6a91b0331fc432e975b13be 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -548,7 +548,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
        val |= intel_psr2_get_tp_time(intel_dp);
 
        /* Wa_22012278275:adl-p */
-       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D1)) {
+       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
                static const u8 map[] = {
                        2, /* 5 lines */
                        1, /* 6 lines */
@@ -595,7 +595,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
        if (intel_dp->psr.psr2_sel_fetch_enabled) {
                /* Wa_1408330847 */
-               if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+               if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
                        intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
                                     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
                                     DIS_RAM_BYPASS_PSR2_MAN_TRACK);
@@ -735,7 +735,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
                return;
 
        /* Wa_16011303918:adl-p */
-       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
                return;
 
        /*
@@ -782,7 +782,7 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
        }
 
        /* Wa_14010254185 Wa_14010103792 */
-       if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
+       if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
                drm_dbg_kms(&dev_priv->drm,
                            "PSR2 sel fetch not enabled, missing the implementation of WAs\n");
                return false;
@@ -945,7 +945,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 
        /* Wa_2209313811 */
        if (!crtc_state->enable_psr2_sel_fetch &&
-           IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) {
+           IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
                drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n");
                return false;
        }
@@ -972,7 +972,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 
        /* Wa_16011303918:adl-p */
        if (crtc_state->vrr.enable &&
-           IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) {
+           IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
                drm_dbg_kms(&dev_priv->drm,
                            "PSR2 not enabled, not compatible with HW stepping + VRR\n");
                return false;
@@ -1166,7 +1166,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
                             IGNORE_PSR2_HW_TRACKING : 0);
 
        /* Wa_16011168373:adl-p */
-       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
+       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
            intel_dp->psr.psr2_enabled)
                intel_de_rmw(dev_priv,
                             TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
@@ -1346,12 +1346,12 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 
        /* Wa_1408330847 */
        if (intel_dp->psr.psr2_sel_fetch_enabled &&
-           IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+           IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
                intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
                             DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
 
        /* Wa_16011168373:adl-p */
-       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) &&
+       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
            intel_dp->psr.psr2_enabled)
                intel_de_rmw(dev_priv,
                             TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 628b678d9a71c4e814d2327815b194adcd3c498a..3ad04bf2a0fd4cbbdd15691eeecbffc99d7b9573 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1910,11 +1910,11 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
 {
        /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
        if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
-           IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
+           IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D0))
                return false;
 
        /* Wa_22011186057 */
-       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
                return false;
 
        return plane_id < PLANE_SPRITE4;
@@ -1938,7 +1938,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
        case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
        case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
                /* Wa_22011186057 */
-               if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+               if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
                        return false;
                break;
        default:
@@ -1995,7 +1995,7 @@ static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
                                            enum plane_id plane_id)
 {
        /* Wa_22011186057 */
-       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
                return adlp_step_a_plane_format_modifiers;
        else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
                return gen12_plane_format_modifiers_mc_ccs;

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index aa05c40139b22ee7a50b489ff0bfa397120e3da8..be90f5513144c48812bb28e41f783eac34e003c0 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1268,7 +1268,7 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
 
 #define IS_DISPLAY_STEP(__i915, since, until) \
        (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
-        INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) <= (until))
+        INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
 
 #define IS_GT_STEP(__i915, since, until) \
        (drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index dd63dd2c45ad2445dc34413f8477caafb4a10a32..5c83b2ec69da49a495db22586660a9add7219629 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -262,7 +262,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
        enum pipe pipe;
 
        /* Wa_14011765242: adl-s A0,A1 */
-       if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A1))
+       if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
                for_each_pipe(dev_priv, pipe)
                        runtime->num_scalers[pipe] = 0;
        else if (GRAPHICS_VER(dev_priv) >= 10) {

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3925e90c52c4790f38a4fe1c7c0a6fc451f04b7a..a1d67feb16316af23fb4bdecba373e80208feb10 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7361,7 +7361,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
                           ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 
        /* Wa_1409825376:tgl (pre-prod)*/
-       if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1))
+       if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
                intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
                           TGL_VRH_GATING_DIS);