drm/amd/display: Allow asic specific FSFT timing optimization

[Why]
Each asic can optimize best based on its capabilities

[How]
Optimizing timing for a new pixel clock

Signed-off-by: Reza Amini <Reza.Amini@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 10d69ada88e3d78426a2c46b054a70e34afcefd5..0257a900fe2bb779cd1d351e66e8dffa0079fe6d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -246,20 +246,18 @@ struct dc_stream_status *dc_stream_get_status(
 
 #ifndef TRIM_FSFT
 /**
- * dc_optimize_timing() - dc to optimize timing
+ * dc_optimize_timing_for_fsft() - dc to optimize timing
  */
-bool dc_optimize_timing(
-       struct dc_crtc_timing *timing,
+bool dc_optimize_timing_for_fsft(
+       struct dc_stream_state *pStream,
        unsigned int max_input_rate_in_khz)
 {
-       //optimization is expected to assing a value to these:
-       //timing->pix_clk_100hz
-       //timing->v_front_porch
-       //timing->v_total
-       //timing->fast_transport_output_rate_100hz;
-       timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz;
+       struct dc  *dc;
 
-       return true;
+       dc = pStream->ctx->dc;
+
+       return (dc->hwss.optimize_timing_for_fsft &&
+               dc->hwss.optimize_timing_for_fsft(dc, &pStream->timing, max_input_rate_in_khz));
 }
 #endif
 

diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index e4e85a1594624ce98ae5178d1ae12e33ddc1a565..633442bc7ef268bd094e75ae9a8583700b1d86aa 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -424,8 +424,8 @@ struct dc_stream_status *dc_stream_get_status(
        struct dc_stream_state *dc_stream);
 
 #ifndef TRIM_FSFT
-bool dc_optimize_timing(
-       struct dc_crtc_timing *timing,
+bool dc_optimize_timing_for_fsft(
+       struct dc_stream_state *pStream,
        unsigned int max_input_rate_in_khz);
 #endif
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 7725a406c16ee245b26e9a7aa1def9f3c14a7e21..66180b4332f1d6b410d80602e5c606dfe8f1a866 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2498,3 +2498,30 @@ void dcn20_fpga_init_hw(struct dc *dc)
                tg->funcs->tg_init(tg);
        }
 }
+#ifndef TRIM_FSFT
+bool dcn20_optimize_timing_for_fsft(struct dc *dc,
+               struct dc_crtc_timing *timing,
+               unsigned int max_input_rate_in_khz)
+{
+       unsigned int old_v_front_porch;
+       unsigned int old_v_total;
+       unsigned int max_input_rate_in_100hz;
+       unsigned long long new_v_total;
+
+       max_input_rate_in_100hz = max_input_rate_in_khz * 10;
+       if (max_input_rate_in_100hz < timing->pix_clk_100hz)
+               return false;
+
+       old_v_total = timing->v_total;
+       old_v_front_porch = timing->v_front_porch;
+
+       timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz;
+       timing->pix_clk_100hz = max_input_rate_in_100hz;
+
+       new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz);
+
+       timing->v_total = new_v_total;
+       timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total);
+       return true;
+}
+#endif

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
index 63ce763f148ec30bdd737ca40ecf74bdfc21c5f2..83220e34c1a92d22b11bd21ad39db6f09aef35ae 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
@@ -132,5 +132,10 @@ int dcn20_init_sys_ctx(struct dce_hwseq *hws,
                struct dc *dc,
                struct dc_phy_addr_space_config *pa_config);
 
+#ifndef TRIM_FSFT
+bool dcn20_optimize_timing_for_fsft(struct dc *dc,
+               struct dc_crtc_timing *timing,
+               unsigned int max_input_rate_in_khz);
+#endif
 #endif /* __DC_HWSS_DCN20_H__ */
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
index 2380392b916ed3a4a50fcf490fb07a43367b56dd..3dde6f26de47426796156c937a5fa1775c5d519c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
@@ -88,6 +88,9 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
        .set_backlight_level = dce110_set_backlight_level,
        .set_abm_immediate_disable = dce110_set_abm_immediate_disable,
        .set_pipe = dce110_set_pipe,
+#ifndef TRIM_FSFT
+       .optimize_timing_for_fsft = dcn20_optimize_timing_for_fsft,
+#endif
 };
 
 static const struct hwseq_private_funcs dcn20_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
index 177d0dc8927a6936786344a351d90d68b742ebfb..b187f71afa652535af945638e34d3b64ca8751fd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
@@ -92,6 +92,9 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
        .set_backlight_level = dcn21_set_backlight_level,
        .set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
        .set_pipe = dcn21_set_pipe,
+#ifndef TRIM_FSFT
+       .optimize_timing_for_fsft = dcn20_optimize_timing_for_fsft,
+#endif
 };
 
 static const struct hwseq_private_funcs dcn21_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 720ce5e458d80ad65b83844d57089fc606995ea3..3c986717dcd5621f14218724106c1c59ec953842 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -116,6 +116,11 @@ struct hw_sequencer_funcs {
        void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
                        int num_pipes,
                        const struct dc_static_screen_params *events);
+#ifndef TRIM_FSFT
+       bool (*optimize_timing_for_fsft)(struct dc *dc,
+                       struct dc_crtc_timing *timing,
+                       unsigned int max_input_rate_in_khz);
+#endif
 
        /* Stream Related */
        void (*enable_stream)(struct pipe_ctx *pipe_ctx);

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 7a2500fbf3f2964380b5c2a9e0ac47af0c963431..81820f3d6b3b473c9fe9da2f84fd0fa8204f0458 100644 (file)
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -829,10 +829,13 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
        switch (packet_type) {
        case PACKET_TYPE_FS_V3:
 #ifndef TRIM_FSFT
+               // always populate with pixel rate.
                build_vrr_infopacket_v3(
                                stream->signal, vrr,
                                stream->timing.flags.FAST_TRANSPORT,
-                               stream->timing.fast_transport_output_rate_100hz,
+                               (stream->timing.flags.FAST_TRANSPORT) ?
+                                               stream->timing.fast_transport_output_rate_100hz :
+                                               stream->timing.pix_clk_100hz,
                                app_tf, infopacket);
 #else
                build_vrr_infopacket_v3(stream->signal, vrr, app_tf, infopacket);