]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/commitdiff
drm/tegra: dc: Add Tegra194 support
authorThierry Reding <treding@nvidia.com>
Fri, 21 Sep 2018 10:27:44 +0000 (12:27 +0200)
committerThierry Reding <treding@nvidia.com>
Wed, 26 Sep 2018 14:04:39 +0000 (16:04 +0200)
The display controllers found on Tegra194 are almost identical to those
found on Tegra186.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/drm/tegra/dc.c
drivers/gpu/drm/tegra/dc.h
drivers/gpu/drm/tegra/drm.c

index 7e36ca204cbbda84bb5eee33458bf2bff65a9ce0..f80e82e164759457ae02f85ecb7354930c0f344f 100644 (file)
@@ -2256,8 +2256,59 @@ static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
        .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
 };
 
+static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
+       {
+               .index = 0,
+               .dc = 0,
+               .windows = (const unsigned int[]) { 0 },
+               .num_windows = 1,
+       }, {
+               .index = 1,
+               .dc = 1,
+               .windows = (const unsigned int[]) { 1 },
+               .num_windows = 1,
+       }, {
+               .index = 2,
+               .dc = 1,
+               .windows = (const unsigned int[]) { 2 },
+               .num_windows = 1,
+       }, {
+               .index = 3,
+               .dc = 2,
+               .windows = (const unsigned int[]) { 3 },
+               .num_windows = 1,
+       }, {
+               .index = 4,
+               .dc = 2,
+               .windows = (const unsigned int[]) { 4 },
+               .num_windows = 1,
+       }, {
+               .index = 5,
+               .dc = 2,
+               .windows = (const unsigned int[]) { 5 },
+               .num_windows = 1,
+       },
+};
+
+static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
+       .supports_background_color = true,
+       .supports_interlacing = true,
+       .supports_cursor = true,
+       .supports_block_linear = true,
+       .has_legacy_blending = false,
+       .pitch_align = 64,
+       .has_powergate = false,
+       .coupled_pm = false,
+       .has_nvdisplay = true,
+       .wgrps = tegra194_dc_wgrps,
+       .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
+};
+
 static const struct of_device_id tegra_dc_of_match[] = {
        {
+               .compatible = "nvidia,tegra194-dc",
+               .data = &tegra194_dc_soc_info,
+       }, {
                .compatible = "nvidia,tegra186-dc",
                .data = &tegra186_dc_soc_info,
        }, {
index e96f582ca692e8df51bcf86a19b428fd0d57ffb0..1256dfb6b2f5cf7211d2a0b7aae2907dfd746b27 100644 (file)
@@ -300,7 +300,7 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
 #define SOR1_TIMING_CYA        (1 << 27)
 #define CURSOR_ENABLE  (1 << 16)
 
-#define SOR_ENABLE(x)  (1 << (25 + (x)))
+#define SOR_ENABLE(x)  (1 << (25 + (((x) > 1) ? ((x) + 1) : (x))))
 
 #define DC_DISP_DISP_MEM_HIGH_PRIORITY         0x403
 #define CURSOR_THRESHOLD(x)   (((x) & 0x03) << 24)
index 4e40ffd2b32e23a953c57d9a249393f9e34fa81f..0ed6fa8ac4462c880d04406301c5d17b6790a495 100644 (file)
@@ -1256,6 +1256,7 @@ static const struct of_device_id host1x_drm_subdevs[] = {
        { .compatible = "nvidia,tegra186-sor1", },
        { .compatible = "nvidia,tegra186-vic", },
        { .compatible = "nvidia,tegra194-display", },
+       { .compatible = "nvidia,tegra194-dc", },
        { /* sentinel */ }
 };