]> git.proxmox.com Git - mirror_ubuntu-kernels.git/commitdiff
drm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2)
authorHarry Wentland <harry.wentland@amd.com>
Fri, 22 Feb 2019 21:52:52 +0000 (16:52 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Sat, 22 Jun 2019 14:34:07 +0000 (09:34 -0500)
Enable DCN2 support in DM (Display Manager).

v2: fix spurious raven change (Alex)

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/Kconfig
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

index 5c826faae240c7a1d06944181a93ad5f89bc3be3..df951cbb4c6c4d9d1c6409d7806cc7edfc8b1c10 100644 (file)
@@ -16,6 +16,15 @@ config DRM_AMD_DC_DCN1_0
        help
          RV family support for display engine
 
+config DRM_AMD_DC_DCN2_0
+       bool "DCN 2.0 family"
+       default y
+       depends on DRM_AMD_DC && X86
+       depends on DRM_AMD_DC_DCN1_0
+       help
+           Choose this option if you want to have
+           Navi support for display engine
+
 config DEBUG_KERNEL_DC
        bool "Enable kgdb break in DC"
        depends on DRM_AMD_DC
index eeaf84e40dc1ecd409bf767cd0a27d730cb73a34..5971aef4f033e616be1fe8ca2ebb7200300fd2f2 100644 (file)
@@ -666,6 +666,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
        case CHIP_VEGA10:
        case CHIP_VEGA12:
        case CHIP_VEGA20:
+       case CHIP_NAVI10:
                return 0;
        case CHIP_RAVEN:
                if (ASICREV_IS_PICASSO(adev->external_rev_id))
@@ -2210,6 +2211,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
                break;
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
        case CHIP_RAVEN:
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+       case CHIP_NAVI10:
+#endif
                if (dcn10_register_irq_handlers(dm->adev)) {
                        DRM_ERROR("DM: Failed to initialize IRQ\n");
                        goto fail;
@@ -2362,6 +2366,13 @@ static int dm_early_init(void *handle)
                adev->mode_info.num_hpd = 4;
                adev->mode_info.num_dig = 4;
                break;
+#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+       case CHIP_NAVI10:
+               adev->mode_info.num_crtc = 6;
+               adev->mode_info.num_hpd = 6;
+               adev->mode_info.num_dig = 6;
+               break;
 #endif
        default:
                DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
@@ -2655,6 +2666,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
        if (adev->asic_type == CHIP_VEGA10 ||
            adev->asic_type == CHIP_VEGA12 ||
            adev->asic_type == CHIP_VEGA20 ||
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+           adev->asic_type == CHIP_NAVI10 ||
+#endif
            adev->asic_type == CHIP_RAVEN) {
                /* Fill GFX9 params */
                tiling_info->gfx9.num_pipes =
index 7258c992a2bf7f37a969e7f5b3233c6bd240ad7f..75b6a2ac910b9eedb8896c25a8c0f870fd27cb1a 100644 (file)
@@ -166,7 +166,7 @@ int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc)
         */
        stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
        ret = mod_color_calculate_regamma_params(stream->out_transfer_func,
-                       gamma, true, adev->asic_type <= CHIP_RAVEN, NULL);
+                       gamma, true, adev->asic_type <= CHIP_NAVI10, NULL);
 
        if (gamma)
                dc_gamma_release(&gamma);