DEF_HELPER_FLAGS_3(carry, TCG_CALL_PURE | TCG_CALL_CONST, i32, i32, i32, i32)
DEF_HELPER_2(cmp, i32, i32, i32)
DEF_HELPER_2(cmpu, i32, i32, i32)
+DEF_HELPER_FLAGS_1(clz, TCG_CALL_PURE | TCG_CALL_CONST, i32, i32)
DEF_HELPER_2(divs, i32, i32, i32)
DEF_HELPER_2(divu, i32, i32, i32)
return t;
}
+uint32_t helper_clz(uint32_t t0)
+{
+ return clz32(t0);
+}
+
uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
{
uint32_t ncf;
return;
}
break;
+ case 0xe0:
+ if ((dc->tb_flags & MSR_EE_FLAG)
+ && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
+ && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
+ tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
+ t_gen_raise_exception(dc, EXCP_HW_EXCP);
+ }
+ if (dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR) {
+ gen_helper_clz(cpu_R[dc->rd], cpu_R[dc->ra]);
+ }
+ break;
default:
cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
dc->pc, op, dc->rd, dc->ra, dc->rb);