crypto: qat - fix CSR access

Do not mask the AE number with the AE mask when accessing the AE local
CSRs. Bit 12 of the local CSR address is the start of AE number so just
take out the AE mask here.

Signed-off-by: Jack Xu <jack.xu@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/qat/qat_common/icp_qat_hal.h b/drivers/crypto/qat/qat_common/icp_qat_hal.h
index c0e9fc0c93dd5725d3f912eaddbaa3cec2542430..b48b313623feacd97426c1a076ff4d97f25e4916 100644 (file)
--- a/drivers/crypto/qat/qat_common/icp_qat_hal.h
+++ b/drivers/crypto/qat/qat_common/icp_qat_hal.h
@@ -94,15 +94,13 @@ enum fcu_sts {
 #define SET_GLB_CSR(handle, csr, val) SET_CAP_CSR(handle, csr + GLOBAL_CSR, val)
 #define GET_GLB_CSR(handle, csr) GET_CAP_CSR(handle, GLOBAL_CSR + csr)
 #define AE_CSR(handle, ae) \
-       ((char __iomem *)handle->hal_cap_ae_local_csr_addr_v + \
-       ((ae & handle->hal_handle->ae_mask) << 12))
+       ((char __iomem *)handle->hal_cap_ae_local_csr_addr_v + (ae << 12))
 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & csr))
 #define SET_AE_CSR(handle, ae, csr, val) \
        ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)
 #define AE_XFER(handle, ae) \
-       ((char __iomem *)handle->hal_cap_ae_xfer_csr_addr_v + \
-       ((ae & handle->hal_handle->ae_mask) << 12))
+       ((char __iomem *)handle->hal_cap_ae_xfer_csr_addr_v + (ae << 12))
 #define AE_XFER_ADDR(handle, ae, reg) (AE_XFER(handle, ae) + \
        ((reg & 0xff) << 2))
 #define SET_AE_XFER(handle, ae, reg, val) \