+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-// Copyright (C) 2014 - 2020 Intel Corporation
-
-#include <linux/device.h>
-#include <linux/module.h>
-
-#include <media/ipu-isys.h>
-#include <media/media-entity.h>
-#include <media/v4l2-device.h>
-
-#include "ipu.h"
-#include "ipu-bus.h"
-#include "ipu-isys.h"
-#include "ipu-isys-csi2-be.h"
-#include "ipu-isys-subdev.h"
-#include "ipu-isys-video.h"
-
-/*
- * Raw bayer format pixel order MUST BE MAINTAINED in groups of four codes.
- * Otherwise pixel order calculation below WILL BREAK!
- */
-static const u32 csi2_be_supported_codes_pad[] = {
- MEDIA_BUS_FMT_SBGGR12_1X12,
- MEDIA_BUS_FMT_SGBRG12_1X12,
- MEDIA_BUS_FMT_SGRBG12_1X12,
- MEDIA_BUS_FMT_SRGGB12_1X12,
- MEDIA_BUS_FMT_SBGGR10_1X10,
- MEDIA_BUS_FMT_SGBRG10_1X10,
- MEDIA_BUS_FMT_SGRBG10_1X10,
- MEDIA_BUS_FMT_SRGGB10_1X10,
- MEDIA_BUS_FMT_SBGGR8_1X8,
- MEDIA_BUS_FMT_SGBRG8_1X8,
- MEDIA_BUS_FMT_SGRBG8_1X8,
- MEDIA_BUS_FMT_SRGGB8_1X8,
- 0,
-};
-
-static const u32 *csi2_be_supported_codes[] = {
- csi2_be_supported_codes_pad,
- csi2_be_supported_codes_pad,
-};
-
-static struct v4l2_subdev_internal_ops csi2_be_sd_internal_ops = {
- .open = ipu_isys_subdev_open,
- .close = ipu_isys_subdev_close,
-};
-
-static const struct v4l2_subdev_core_ops csi2_be_sd_core_ops = {
-};
-
-static const struct v4l2_ctrl_config compression_ctrl_cfg = {
- .ops = NULL,
- .id = V4L2_CID_IPU_ISYS_COMPRESSION,
- .name = "ISYS CSI-BE compression",
- .type = V4L2_CTRL_TYPE_BOOLEAN,
- .min = 0,
- .max = 1,
- .step = 1,
- .def = 0,
-};
-
-static int set_stream(struct v4l2_subdev *sd, int enable)
-{
- return 0;
-}
-
-static const struct v4l2_subdev_video_ops csi2_be_sd_video_ops = {
- .s_stream = set_stream,
-};
-
-static int __subdev_link_validate(struct v4l2_subdev *sd,
- struct media_link *link,
- struct v4l2_subdev_format *source_fmt,
- struct v4l2_subdev_format *sink_fmt)
-{
- struct ipu_isys_pipeline *ip = container_of(sd->entity.pipe,
- struct ipu_isys_pipeline,
- pipe);
-
- ip->csi2_be = to_ipu_isys_csi2_be(sd);
- return ipu_isys_subdev_link_validate(sd, link, source_fmt, sink_fmt);
-}
-
-static int get_supported_code_index(u32 code)
-{
- int i;
-
- for (i = 0; csi2_be_supported_codes_pad[i]; i++) {
- if (csi2_be_supported_codes_pad[i] == code)
- return i;
- }
- return -EINVAL;
-}
-
-static int ipu_isys_csi2_be_set_sel(struct v4l2_subdev *sd,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel)
-{
- struct ipu_isys_subdev *asd = to_ipu_isys_subdev(sd);
- struct media_pad *pad = &asd->sd.entity.pads[sel->pad];
-
- if (sel->target == V4L2_SEL_TGT_CROP &&
- pad->flags & MEDIA_PAD_FL_SOURCE &&
- asd->valid_tgts[CSI2_BE_PAD_SOURCE].crop) {
- struct v4l2_mbus_framefmt *ffmt =
- __ipu_isys_get_ffmt(sd, cfg, sel->pad, sel->which);
- struct v4l2_rect *r = __ipu_isys_get_selection
- (sd, cfg, sel->target, CSI2_BE_PAD_SINK, sel->which);
-
- if (get_supported_code_index(ffmt->code) < 0) {
- /* Non-bayer formats can't be single line cropped */
- sel->r.left &= ~1;
- sel->r.top &= ~1;
-
- /* Non-bayer formats can't pe padded at all */
- sel->r.width = clamp(sel->r.width,
- IPU_ISYS_MIN_WIDTH, r->width);
- } else {
- sel->r.width = clamp(sel->r.width,
- IPU_ISYS_MIN_WIDTH,
- IPU_ISYS_MAX_WIDTH);
- }
-
- /*
- * Vertical padding is not supported, height is
- * restricted by sink pad resolution.
- */
- sel->r.height = clamp(sel->r.height, IPU_ISYS_MIN_HEIGHT,
- r->height);
- *__ipu_isys_get_selection(sd, cfg, sel->target, sel->pad,
- sel->which) = sel->r;
- ipu_isys_subdev_fmt_propagate
- (sd, cfg, NULL, &sel->r,
- IPU_ISYS_SUBDEV_PROP_TGT_SOURCE_CROP,
- sel->pad, sel->which);
- return 0;
- }
- return ipu_isys_subdev_set_sel(sd, cfg, sel);
-}
-
-static const struct v4l2_subdev_pad_ops csi2_be_sd_pad_ops = {
- .link_validate = __subdev_link_validate,
- .get_fmt = ipu_isys_subdev_get_ffmt,
- .set_fmt = ipu_isys_subdev_set_ffmt,
- .get_selection = ipu_isys_subdev_get_sel,
- .set_selection = ipu_isys_csi2_be_set_sel,
- .enum_mbus_code = ipu_isys_subdev_enum_mbus_code,
-};
-
-static struct v4l2_subdev_ops csi2_be_sd_ops = {
- .core = &csi2_be_sd_core_ops,
- .video = &csi2_be_sd_video_ops,
- .pad = &csi2_be_sd_pad_ops,
-};
-
-static struct media_entity_operations csi2_be_entity_ops = {
- .link_validate = v4l2_subdev_link_validate,
-};
-
-static void csi2_be_set_ffmt(struct v4l2_subdev *sd,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_format *fmt)
-{
- struct ipu_isys_csi2 *csi2 = to_ipu_isys_csi2(sd);
- struct v4l2_mbus_framefmt *ffmt =
- __ipu_isys_get_ffmt(sd, cfg, fmt->pad, fmt->which);
-
- switch (fmt->pad) {
- case CSI2_BE_PAD_SINK:
- if (fmt->format.field != V4L2_FIELD_ALTERNATE)
- fmt->format.field = V4L2_FIELD_NONE;
- *ffmt = fmt->format;
-
- ipu_isys_subdev_fmt_propagate
- (sd, cfg, &fmt->format, NULL,
- IPU_ISYS_SUBDEV_PROP_TGT_SINK_FMT, fmt->pad, fmt->which);
- return;
- case CSI2_BE_PAD_SOURCE: {
- struct v4l2_mbus_framefmt *sink_ffmt =
- __ipu_isys_get_ffmt(sd, cfg, CSI2_BE_PAD_SINK,
- fmt->which);
- struct v4l2_rect *r =
- __ipu_isys_get_selection(sd, cfg, V4L2_SEL_TGT_CROP,
- CSI2_BE_PAD_SOURCE,
- fmt->which);
- struct ipu_isys_subdev *asd = to_ipu_isys_subdev(sd);
- u32 code = sink_ffmt->code;
- int idx = get_supported_code_index(code);
-
- if (asd->valid_tgts[CSI2_BE_PAD_SOURCE].crop && idx >= 0) {
- int crop_info = 0;
-
- if (r->top & 1)
- crop_info |= CSI2_BE_CROP_VER;
- if (r->left & 1)
- crop_info |= CSI2_BE_CROP_HOR;
- code = csi2_be_supported_codes_pad
- [((idx & CSI2_BE_CROP_MASK) ^ crop_info)
- + (idx & ~CSI2_BE_CROP_MASK)];
- }
- ffmt->width = r->width;
- ffmt->height = r->height;
- ffmt->code = code;
- ffmt->field = sink_ffmt->field;
- return;
- }
- default:
- dev_err(&csi2->isys->adev->dev, "Unknown pad type\n");
- WARN_ON(1);
- }
-}
-
-void ipu_isys_csi2_be_cleanup(struct ipu_isys_csi2_be *csi2_be)
-{
- v4l2_ctrl_handler_free(&csi2_be->av.ctrl_handler);
- v4l2_device_unregister_subdev(&csi2_be->asd.sd);
- ipu_isys_subdev_cleanup(&csi2_be->asd);
- ipu_isys_video_cleanup(&csi2_be->av);
-}
-
-int ipu_isys_csi2_be_init(struct ipu_isys_csi2_be *csi2_be,
- struct ipu_isys *isys)
-{
- struct v4l2_subdev_format fmt = {
- .which = V4L2_SUBDEV_FORMAT_ACTIVE,
- .pad = CSI2_BE_PAD_SINK,
- .format = {
- .width = 4096,
- .height = 3072,
- },
- };
- struct v4l2_subdev_selection sel = {
- .which = V4L2_SUBDEV_FORMAT_ACTIVE,
- .pad = CSI2_BE_PAD_SOURCE,
- .target = V4L2_SEL_TGT_CROP,
- .r = {
- .width = fmt.format.width,
- .height = fmt.format.height,
- },
- };
- int rval;
-
- csi2_be->asd.sd.entity.ops = &csi2_be_entity_ops;
- csi2_be->asd.isys = isys;
-
- rval = ipu_isys_subdev_init(&csi2_be->asd, &csi2_be_sd_ops, 0,
- NR_OF_CSI2_BE_PADS,
- NR_OF_CSI2_BE_SOURCE_PADS,
- NR_OF_CSI2_BE_SINK_PADS, 0);
- if (rval)
- goto fail;
-
- csi2_be->asd.pad[CSI2_BE_PAD_SINK].flags = MEDIA_PAD_FL_SINK
- | MEDIA_PAD_FL_MUST_CONNECT;
- csi2_be->asd.pad[CSI2_BE_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
- csi2_be->asd.valid_tgts[CSI2_BE_PAD_SOURCE].crop = true;
- csi2_be->asd.set_ffmt = csi2_be_set_ffmt;
-
- BUILD_BUG_ON(ARRAY_SIZE(csi2_be_supported_codes) != NR_OF_CSI2_BE_PADS);
- csi2_be->asd.supported_codes = csi2_be_supported_codes;
- csi2_be->asd.be_mode = IPU_BE_RAW;
- csi2_be->asd.isl_mode = IPU_ISL_CSI2_BE;
-
- ipu_isys_subdev_set_ffmt(&csi2_be->asd.sd, NULL, &fmt);
- ipu_isys_csi2_be_set_sel(&csi2_be->asd.sd, NULL, &sel);
-
- csi2_be->asd.sd.internal_ops = &csi2_be_sd_internal_ops;
- snprintf(csi2_be->asd.sd.name, sizeof(csi2_be->asd.sd.name),
- IPU_ISYS_ENTITY_PREFIX " CSI2 BE");
- snprintf(csi2_be->av.vdev.name, sizeof(csi2_be->av.vdev.name),
- IPU_ISYS_ENTITY_PREFIX " CSI2 BE capture");
- csi2_be->av.aq.css_pin_type = IPU_FW_ISYS_PIN_TYPE_RAW_NS;
- v4l2_set_subdevdata(&csi2_be->asd.sd, &csi2_be->asd);
- rval = v4l2_device_register_subdev(&isys->v4l2_dev, &csi2_be->asd.sd);
- if (rval) {
- dev_info(&isys->adev->dev, "can't register v4l2 subdev\n");
- goto fail;
- }
-
- csi2_be->av.isys = isys;
- csi2_be->av.pfmts = ipu_isys_pfmts;
- csi2_be->av.try_fmt_vid_mplane =
- ipu_isys_video_try_fmt_vid_mplane_default;
- csi2_be->av.prepare_fw_stream =
- ipu_isys_prepare_fw_cfg_default;
- csi2_be->av.aq.buf_prepare = ipu_isys_buf_prepare;
- csi2_be->av.aq.fill_frame_buff_set_pin =
- ipu_isys_buffer_to_fw_frame_buff_pin;
- csi2_be->av.aq.link_fmt_validate = ipu_isys_link_fmt_validate;
- csi2_be->av.aq.vbq.buf_struct_size =
- sizeof(struct ipu_isys_video_buffer);
-
- /* create v4l2 ctrl for csi-be video node */
- rval = v4l2_ctrl_handler_init(&csi2_be->av.ctrl_handler, 0);
- if (rval) {
- dev_err(&isys->adev->dev,
- "failed to init v4l2 ctrl handler for csi2_be\n");
- goto fail;
- }
-
- csi2_be->av.compression_ctrl =
- v4l2_ctrl_new_custom(&csi2_be->av.ctrl_handler,
- &compression_ctrl_cfg, NULL);
- if (!csi2_be->av.compression_ctrl) {
- dev_err(&isys->adev->dev,
- "failed to create CSI-BE cmprs ctrl\n");
- goto fail;
- }
- csi2_be->av.compression = 0;
- csi2_be->av.vdev.ctrl_handler = &csi2_be->av.ctrl_handler;
-
- rval = ipu_isys_video_init(&csi2_be->av, &csi2_be->asd.sd.entity,
- CSI2_BE_PAD_SOURCE, MEDIA_PAD_FL_SINK, 0);
- if (rval) {
- dev_info(&isys->adev->dev, "can't init video node\n");
- goto fail;
- }
-
- return 0;
-
-fail:
- ipu_isys_csi2_be_cleanup(csi2_be);
-
- return rval;
-}
container_of(to_ipu_isys_subdev(sd), \
struct ipu_isys_csi2_be_soc, asd)
-int ipu_isys_csi2_be_init(struct ipu_isys_csi2_be *csi2_be,
- struct ipu_isys *isys);
int ipu_isys_csi2_be_soc_init(struct ipu_isys_csi2_be_soc *csi2_be_soc,
struct ipu_isys *isys, int index);
-void ipu_isys_csi2_be_cleanup(struct ipu_isys_csi2_be *csi2_be);
void ipu_isys_csi2_be_soc_cleanup(struct ipu_isys_csi2_be_soc *csi2_be);
#endif /* IPU_ISYS_CSI2_BE_H */
v4l2_device_unregister_subdev(&csi2->asd.sd);
ipu_isys_subdev_cleanup(&csi2->asd);
- ipu_isys_video_cleanup(&csi2->av);
csi2->isys = NULL;
}
__ipu_isys_subdev_set_ffmt(&csi2->asd.sd, NULL, &fmt);
mutex_unlock(&csi2->asd.mutex);
- snprintf(csi2->av.vdev.name, sizeof(csi2->av.vdev.name),
- IPU_ISYS_ENTITY_PREFIX " CSI-2 %u capture", index);
- csi2->av.isys = isys;
- csi2->av.aq.css_pin_type = IPU_FW_ISYS_PIN_TYPE_MIPI;
- csi2->av.pfmts = ipu_isys_pfmts_packed;
- csi2->av.try_fmt_vid_mplane = csi2_try_fmt;
- csi2->av.prepare_fw_stream =
- ipu_isys_prepare_fw_cfg_default;
- csi2->av.packed = true;
- csi2->av.line_header_length =
- IPU_ISYS_CSI2_LONG_PACKET_HEADER_SIZE;
- csi2->av.line_footer_length =
- IPU_ISYS_CSI2_LONG_PACKET_FOOTER_SIZE;
- csi2->av.aq.buf_prepare = ipu_isys_buf_prepare;
- csi2->av.aq.fill_frame_buff_set_pin =
- ipu_isys_buffer_to_fw_frame_buff_pin;
- csi2->av.aq.link_fmt_validate =
- ipu_isys_link_fmt_validate;
- csi2->av.aq.vbq.buf_struct_size =
- sizeof(struct ipu_isys_video_buffer);
-
- rval = ipu_isys_video_init(&csi2->av,
- &csi2->asd.sd.entity,
- CSI2_PAD_SOURCE,
- MEDIA_PAD_FL_SINK, 0);
- if (rval) {
- dev_info(&isys->adev->dev, "can't init video node\n");
- goto fail;
- }
-
return 0;
fail:
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-// Copyright (C) 2013 - 2020 Intel Corporation
-
-#include <linux/device.h>
-#include <linux/module.h>
-
-#include <media/media-entity.h>
-#include <media/v4l2-device.h>
-#include <media/v4l2-event.h>
-
-#include "ipu.h"
-#include "ipu-bus.h"
-#include "ipu-isys.h"
-#include "ipu-isys-subdev.h"
-#include "ipu-isys-tpg.h"
-#include "ipu-isys-video.h"
-#include "ipu-platform-isys-csi2-reg.h"
-
-static const u32 tpg_supported_codes_pad[] = {
- MEDIA_BUS_FMT_SBGGR8_1X8,
- MEDIA_BUS_FMT_SGBRG8_1X8,
- MEDIA_BUS_FMT_SGRBG8_1X8,
- MEDIA_BUS_FMT_SRGGB8_1X8,
- MEDIA_BUS_FMT_SBGGR10_1X10,
- MEDIA_BUS_FMT_SGBRG10_1X10,
- MEDIA_BUS_FMT_SGRBG10_1X10,
- MEDIA_BUS_FMT_SRGGB10_1X10,
- 0,
-};
-
-static const u32 *tpg_supported_codes[] = {
- tpg_supported_codes_pad,
-};
-
-static struct v4l2_subdev_internal_ops tpg_sd_internal_ops = {
- .open = ipu_isys_subdev_open,
- .close = ipu_isys_subdev_close,
-};
-
-static const struct v4l2_subdev_video_ops tpg_sd_video_ops = {
- .s_stream = tpg_set_stream,
-};
-
-static int ipu_isys_tpg_s_ctrl(struct v4l2_ctrl *ctrl)
-{
- struct ipu_isys_tpg *tpg = container_of(container_of(ctrl->handler,
- struct
- ipu_isys_subdev,
- ctrl_handler),
- struct ipu_isys_tpg, asd);
-
- switch (ctrl->id) {
- case V4L2_CID_HBLANK:
- writel(ctrl->val, tpg->base + MIPI_GEN_REG_SYNG_HBLANK_CYC);
- break;
- case V4L2_CID_VBLANK:
- writel(ctrl->val, tpg->base + MIPI_GEN_REG_SYNG_VBLANK_CYC);
- break;
- case V4L2_CID_TEST_PATTERN:
- writel(ctrl->val, tpg->base + MIPI_GEN_REG_TPG_MODE);
- break;
- }
-
- return 0;
-}
-
-static const struct v4l2_ctrl_ops ipu_isys_tpg_ctrl_ops = {
- .s_ctrl = ipu_isys_tpg_s_ctrl,
-};
-
-static s64 ipu_isys_tpg_rate(struct ipu_isys_tpg *tpg, unsigned int bpp)
-{
- return MIPI_GEN_PPC * IPU_ISYS_FREQ / bpp;
-}
-
-static const char *const tpg_mode_items[] = {
- "Ramp",
- "Checkerboard", /* Does not work, disabled. */
- "Frame Based Colour",
-};
-
-static struct v4l2_ctrl_config tpg_mode = {
- .ops = &ipu_isys_tpg_ctrl_ops,
- .id = V4L2_CID_TEST_PATTERN,
- .name = "Test Pattern",
- .type = V4L2_CTRL_TYPE_MENU,
- .min = 0,
- .max = ARRAY_SIZE(tpg_mode_items) - 1,
- .def = 0,
- .menu_skip_mask = 0x2,
- .qmenu = tpg_mode_items,
-};
-
-static const struct v4l2_ctrl_config csi2_header_cfg = {
- .id = V4L2_CID_IPU_STORE_CSI2_HEADER,
- .name = "Store CSI-2 Headers",
- .type = V4L2_CTRL_TYPE_BOOLEAN,
- .min = 0,
- .max = 1,
- .step = 1,
- .def = 1,
-};
-
-static void ipu_isys_tpg_init_controls(struct v4l2_subdev *sd)
-{
- struct ipu_isys_tpg *tpg = to_ipu_isys_tpg(sd);
- int hblank;
- u64 default_pixel_rate;
-
- hblank = 1024;
-
- tpg->hblank = v4l2_ctrl_new_std(&tpg->asd.ctrl_handler,
- &ipu_isys_tpg_ctrl_ops,
- V4L2_CID_HBLANK, 8, 65535, 1, hblank);
-
- tpg->vblank = v4l2_ctrl_new_std(&tpg->asd.ctrl_handler,
- &ipu_isys_tpg_ctrl_ops,
- V4L2_CID_VBLANK, 8, 65535, 1, 1024);
-
- default_pixel_rate = ipu_isys_tpg_rate(tpg, 8);
- tpg->pixel_rate = v4l2_ctrl_new_std(&tpg->asd.ctrl_handler,
- &ipu_isys_tpg_ctrl_ops,
- V4L2_CID_PIXEL_RATE,
- default_pixel_rate,
- default_pixel_rate,
- 1, default_pixel_rate);
- if (tpg->pixel_rate) {
- tpg->pixel_rate->cur.val = default_pixel_rate;
- tpg->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY;
- }
-
- v4l2_ctrl_new_custom(&tpg->asd.ctrl_handler, &tpg_mode, NULL);
- tpg->store_csi2_header =
- v4l2_ctrl_new_custom(&tpg->asd.ctrl_handler,
- &csi2_header_cfg, NULL);
-}
-
-static void tpg_set_ffmt(struct v4l2_subdev *sd,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_format *fmt)
-{
- fmt->format.field = V4L2_FIELD_NONE;
- *__ipu_isys_get_ffmt(sd, cfg, fmt->pad, fmt->which) = fmt->format;
-}
-
-static int ipu_isys_tpg_set_ffmt(struct v4l2_subdev *sd,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_format *fmt)
-{
- struct ipu_isys_tpg *tpg = to_ipu_isys_tpg(sd);
- __u32 code = tpg->asd.ffmt[TPG_PAD_SOURCE].code;
- unsigned int bpp = ipu_isys_mbus_code_to_bpp(code);
- s64 tpg_rate = ipu_isys_tpg_rate(tpg, bpp);
- int rval;
-
- mutex_lock(&tpg->asd.mutex);
- rval = __ipu_isys_subdev_set_ffmt(sd, cfg, fmt);
- mutex_unlock(&tpg->asd.mutex);
-
- if (rval || fmt->which != V4L2_SUBDEV_FORMAT_ACTIVE)
- return rval;
-
- v4l2_ctrl_s_ctrl_int64(tpg->pixel_rate, tpg_rate);
-
- return 0;
-}
-
-static const struct ipu_isys_pixelformat *
-ipu_isys_tpg_try_fmt(struct ipu_isys_video *av,
- struct v4l2_pix_format_mplane *mpix)
-{
- struct media_link *link = list_first_entry(&av->vdev.entity.links,
- struct media_link, list);
- struct v4l2_subdev *sd =
- media_entity_to_v4l2_subdev(link->source->entity);
- struct ipu_isys_tpg *tpg;
-
- if (!sd)
- return NULL;
-
- tpg = to_ipu_isys_tpg(sd);
-
- return ipu_isys_video_try_fmt_vid_mplane(av, mpix,
- v4l2_ctrl_g_ctrl(tpg->store_csi2_header));
-}
-
-static const struct v4l2_subdev_pad_ops tpg_sd_pad_ops = {
- .get_fmt = ipu_isys_subdev_get_ffmt,
- .set_fmt = ipu_isys_tpg_set_ffmt,
- .enum_mbus_code = ipu_isys_subdev_enum_mbus_code,
-};
-
-static int subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
- struct v4l2_event_subscription *sub)
-{
- switch (sub->type) {
-#ifdef IPU_TPG_FRAME_SYNC
- case V4L2_EVENT_FRAME_SYNC:
- return v4l2_event_subscribe(fh, sub, 10, NULL);
-#endif
- case V4L2_EVENT_CTRL:
- return v4l2_ctrl_subscribe_event(fh, sub);
- default:
- return -EINVAL;
- }
-};
-
-/* V4L2 subdev core operations */
-static const struct v4l2_subdev_core_ops tpg_sd_core_ops = {
- .subscribe_event = subscribe_event,
- .unsubscribe_event = v4l2_event_subdev_unsubscribe,
-};
-
-static struct v4l2_subdev_ops tpg_sd_ops = {
- .core = &tpg_sd_core_ops,
- .video = &tpg_sd_video_ops,
- .pad = &tpg_sd_pad_ops,
-};
-
-static struct media_entity_operations tpg_entity_ops = {
- .link_validate = v4l2_subdev_link_validate,
-};
-
-void ipu_isys_tpg_cleanup(struct ipu_isys_tpg *tpg)
-{
- v4l2_device_unregister_subdev(&tpg->asd.sd);
- ipu_isys_subdev_cleanup(&tpg->asd);
- ipu_isys_video_cleanup(&tpg->av);
-}
-
-int ipu_isys_tpg_init(struct ipu_isys_tpg *tpg,
- struct ipu_isys *isys,
- void __iomem *base, void __iomem *sel,
- unsigned int index)
-{
- struct v4l2_subdev_format fmt = {
- .which = V4L2_SUBDEV_FORMAT_ACTIVE,
- .pad = TPG_PAD_SOURCE,
- .format = {
- .width = 4096,
- .height = 3072,
- },
- };
- int rval;
-
- tpg->isys = isys;
- tpg->base = base;
- tpg->sel = sel;
- tpg->index = index;
-
- tpg->asd.sd.entity.ops = &tpg_entity_ops;
- tpg->asd.ctrl_init = ipu_isys_tpg_init_controls;
- tpg->asd.isys = isys;
-
- rval = ipu_isys_subdev_init(&tpg->asd, &tpg_sd_ops, 5,
- NR_OF_TPG_PADS,
- NR_OF_TPG_SOURCE_PADS,
- NR_OF_TPG_SINK_PADS,
- V4L2_SUBDEV_FL_HAS_EVENTS);
- if (rval)
- return rval;
-
- tpg->asd.sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
- tpg->asd.pad[TPG_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
-
- tpg->asd.source = IPU_FW_ISYS_STREAM_SRC_MIPIGEN_PORT0 + index;
- tpg->asd.supported_codes = tpg_supported_codes;
- tpg->asd.set_ffmt = tpg_set_ffmt;
- ipu_isys_subdev_set_ffmt(&tpg->asd.sd, NULL, &fmt);
-
- tpg->asd.sd.internal_ops = &tpg_sd_internal_ops;
- snprintf(tpg->asd.sd.name, sizeof(tpg->asd.sd.name),
- IPU_ISYS_ENTITY_PREFIX " TPG %u", index);
- v4l2_set_subdevdata(&tpg->asd.sd, &tpg->asd);
- rval = v4l2_device_register_subdev(&isys->v4l2_dev, &tpg->asd.sd);
- if (rval) {
- dev_info(&isys->adev->dev, "can't register v4l2 subdev\n");
- goto fail;
- }
-
- snprintf(tpg->av.vdev.name, sizeof(tpg->av.vdev.name),
- IPU_ISYS_ENTITY_PREFIX " TPG %u capture", index);
- tpg->av.isys = isys;
- tpg->av.aq.css_pin_type = IPU_FW_ISYS_PIN_TYPE_MIPI;
- tpg->av.pfmts = ipu_isys_pfmts_packed;
- tpg->av.try_fmt_vid_mplane = ipu_isys_tpg_try_fmt;
- tpg->av.prepare_fw_stream =
- ipu_isys_prepare_fw_cfg_default;
- tpg->av.packed = true;
- tpg->av.line_header_length = IPU_ISYS_CSI2_LONG_PACKET_HEADER_SIZE;
- tpg->av.line_footer_length = IPU_ISYS_CSI2_LONG_PACKET_FOOTER_SIZE;
- tpg->av.aq.buf_prepare = ipu_isys_buf_prepare;
- tpg->av.aq.fill_frame_buff_set_pin =
- ipu_isys_buffer_to_fw_frame_buff_pin;
- tpg->av.aq.link_fmt_validate = ipu_isys_link_fmt_validate;
- tpg->av.aq.vbq.buf_struct_size = sizeof(struct ipu_isys_video_buffer);
-
- rval = ipu_isys_video_init(&tpg->av, &tpg->asd.sd.entity,
- TPG_PAD_SOURCE, MEDIA_PAD_FL_SINK, 0);
- if (rval) {
- dev_info(&isys->adev->dev, "can't init video node\n");
- goto fail;
- }
-
- return 0;
-
-fail:
- ipu_isys_tpg_cleanup(tpg);
-
- return rval;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (C) 2013 - 2020 Intel Corporation */
-
-#ifndef IPU_ISYS_TPG_H
-#define IPU_ISYS_TPG_H
-
-#include <media/media-entity.h>
-#include <media/v4l2-ctrls.h>
-#include <media/v4l2-device.h>
-
-#include "ipu-isys-subdev.h"
-#include "ipu-isys-video.h"
-#include "ipu-isys-queue.h"
-
-struct ipu_isys_tpg_pdata;
-struct ipu_isys;
-
-#define TPG_PAD_SOURCE 0
-#define NR_OF_TPG_PADS 1
-#define NR_OF_TPG_SOURCE_PADS 1
-#define NR_OF_TPG_SINK_PADS 0
-#define NR_OF_TPG_STREAMS 1
-
-/*
- * PPC is 4 pixels for clock for RAW8, RAW10 and RAW12.
- * Source: FW validation test code.
- */
-#define MIPI_GEN_PPC 4
-
-#define MIPI_GEN_REG_COM_ENABLE 0x0
-#define MIPI_GEN_REG_COM_DTYPE 0x4
-/* RAW8, RAW10 or RAW12 */
-#define MIPI_GEN_COM_DTYPE_RAW(n) (((n) - 8) / 2)
-#define MIPI_GEN_REG_COM_VTYPE 0x8
-#define MIPI_GEN_REG_COM_VCHAN 0xc
-#define MIPI_GEN_REG_COM_WCOUNT 0x10
-#define MIPI_GEN_REG_PRBS_RSTVAL0 0x14
-#define MIPI_GEN_REG_PRBS_RSTVAL1 0x18
-#define MIPI_GEN_REG_SYNG_FREE_RUN 0x1c
-#define MIPI_GEN_REG_SYNG_PAUSE 0x20
-#define MIPI_GEN_REG_SYNG_NOF_FRAMES 0x24
-#define MIPI_GEN_REG_SYNG_NOF_PIXELS 0x28
-#define MIPI_GEN_REG_SYNG_NOF_LINES 0x2c
-#define MIPI_GEN_REG_SYNG_HBLANK_CYC 0x30
-#define MIPI_GEN_REG_SYNG_VBLANK_CYC 0x34
-#define MIPI_GEN_REG_SYNG_STAT_HCNT 0x38
-#define MIPI_GEN_REG_SYNG_STAT_VCNT 0x3c
-#define MIPI_GEN_REG_SYNG_STAT_FCNT 0x40
-#define MIPI_GEN_REG_SYNG_STAT_DONE 0x44
-#define MIPI_GEN_REG_TPG_MODE 0x48
-#define MIPI_GEN_REG_TPG_HCNT_MASK 0x4c
-#define MIPI_GEN_REG_TPG_VCNT_MASK 0x50
-#define MIPI_GEN_REG_TPG_XYCNT_MASK 0x54
-#define MIPI_GEN_REG_TPG_HCNT_DELTA 0x58
-#define MIPI_GEN_REG_TPG_VCNT_DELTA 0x5c
-#define MIPI_GEN_REG_TPG_R1 0x60
-#define MIPI_GEN_REG_TPG_G1 0x64
-#define MIPI_GEN_REG_TPG_B1 0x68
-#define MIPI_GEN_REG_TPG_R2 0x6c
-#define MIPI_GEN_REG_TPG_G2 0x70
-#define MIPI_GEN_REG_TPG_B2 0x74
-
-/*
- * struct ipu_isys_tpg
- *
- * @nlanes: number of lanes in the receiver
- */
-struct ipu_isys_tpg {
- struct ipu_isys_tpg_pdata *pdata;
- struct ipu_isys *isys;
- struct ipu_isys_subdev asd;
- struct ipu_isys_video av;
-
- void __iomem *base;
- void __iomem *sel;
- unsigned int index;
- int streaming;
-
- struct v4l2_ctrl *hblank;
- struct v4l2_ctrl *vblank;
- struct v4l2_ctrl *pixel_rate;
- struct v4l2_ctrl *store_csi2_header;
-};
-
-#define to_ipu_isys_tpg(sd) \
- container_of(to_ipu_isys_subdev(sd), \
- struct ipu_isys_tpg, asd)
-#ifdef IPU_TPG_FRAME_SYNC
-void ipu_isys_tpg_sof_event(struct ipu_isys_tpg *tpg);
-void ipu_isys_tpg_eof_event(struct ipu_isys_tpg *tpg);
-#endif
-int ipu_isys_tpg_init(struct ipu_isys_tpg *tpg,
- struct ipu_isys *isys,
- void __iomem *base, void __iomem *sel,
- unsigned int index);
-void ipu_isys_tpg_cleanup(struct ipu_isys_tpg *tpg);
-int tpg_set_stream(struct v4l2_subdev *sd, int enable);
-
-#endif /* IPU_ISYS_TPG_H */
static bool is_external(struct ipu_isys_video *av, struct media_entity *entity)
{
struct v4l2_subdev *sd;
- unsigned int i;
/* All video nodes are ours. */
if (!is_media_entity_v4l2_subdev(entity))
strlen(IPU_ISYS_ENTITY_PREFIX)) != 0)
return true;
- for (i = 0; i < av->isys->pdata->ipdata->tpg.ntpgs &&
- av->isys->tpg[i].isys; i++)
- if (entity == &av->isys->tpg[i].asd.sd.entity)
- return true;
-
return false;
}
if (ip->csi2 && !v4l2_ctrl_g_ctrl(ip->csi2->store_csi2_header))
stream_cfg->input_pins[0].mipi_store_mode =
IPU_FW_ISYS_MIPI_STORE_MODE_DISCARD_LONG_HEADER;
- else if (ip->tpg && !v4l2_ctrl_g_ctrl(ip->tpg->store_csi2_header))
- stream_cfg->input_pins[0].mipi_store_mode =
- IPU_FW_ISYS_MIPI_STORE_MODE_DISCARD_LONG_HEADER;
stream_cfg->src = ip->source;
stream_cfg->vc = 0;
ip->csi2_be = NULL;
ip->csi2_be_soc = NULL;
ip->csi2 = NULL;
- ip->tpg = NULL;
ip->seq_index = 0;
memset(ip->seq, 0, sizeof(ip->seq));
struct ipu_isys_csi2_be *csi2_be;
struct ipu_isys_csi2_be_soc *csi2_be_soc;
struct ipu_isys_csi2 *csi2;
- struct ipu_isys_tpg *tpg;
/*
* Number of capture queues, write access serialised using struct
#include "ipu-dma.h"
#include "ipu-isys.h"
#include "ipu-isys-csi2.h"
-#include "ipu-isys-tpg.h"
#include "ipu-isys-video.h"
#include "ipu-platform-regs.h"
#include "ipu-buttress.h"
static void isys_unregister_subdevices(struct ipu_isys *isys)
{
- const struct ipu_isys_internal_tpg_pdata *tpg =
- &isys->pdata->ipdata->tpg;
const struct ipu_isys_internal_csi2_pdata *csi2 =
&isys->pdata->ipdata->csi2;
unsigned int i;
- ipu_isys_csi2_be_cleanup(&isys->csi2_be);
for (i = 0; i < NR_OF_CSI2_BE_SOC_DEV; i++)
ipu_isys_csi2_be_soc_cleanup(&isys->csi2_be_soc[i]);
- for (i = 0; i < tpg->ntpgs; i++)
- ipu_isys_tpg_cleanup(&isys->tpg[i]);
-
for (i = 0; i < csi2->nports; i++)
ipu_isys_csi2_cleanup(&isys->csi2[i]);
}
static int isys_register_subdevices(struct ipu_isys *isys)
{
- const struct ipu_isys_internal_tpg_pdata *tpg =
- &isys->pdata->ipdata->tpg;
const struct ipu_isys_internal_csi2_pdata *csi2 =
&isys->pdata->ipdata->csi2;
struct ipu_isys_csi2_be_soc *csi2_be_soc;
isys->isr_csi2_bits |= IPU_ISYS_UNISPART_IRQ_CSI2(i);
}
- isys->tpg = devm_kcalloc(&isys->adev->dev, tpg->ntpgs,
- sizeof(*isys->tpg), GFP_KERNEL);
- if (!isys->tpg) {
- rval = -ENOMEM;
- goto fail;
- }
-
- for (i = 0; i < tpg->ntpgs; i++) {
- rval = ipu_isys_tpg_init(&isys->tpg[i], isys,
- isys->pdata->base +
- tpg->offsets[i],
- tpg->sels ? (isys->pdata->base +
- tpg->sels[i]) : NULL, i);
- if (rval)
- goto fail;
- }
-
for (k = 0; k < NR_OF_CSI2_BE_SOC_DEV; k++) {
rval = ipu_isys_csi2_be_soc_init(&isys->csi2_be_soc[k],
isys, k);
}
}
- rval = ipu_isys_csi2_be_init(&isys->csi2_be, isys);
- if (rval) {
- dev_info(&isys->adev->dev,
- "can't register raw csi2 be device\n");
- goto fail;
- }
-
for (i = 0; i < csi2->nports; i++) {
- rval = media_create_pad_link(&isys->csi2[i].asd.sd.entity,
- CSI2_PAD_SOURCE,
- &isys->csi2_be.asd.sd.entity,
- CSI2_BE_PAD_SINK, 0);
- if (rval) {
- dev_info(&isys->adev->dev,
- "can't create link csi2 <=> csi2_be\n");
- goto fail;
- }
for (k = 0; k < NR_OF_CSI2_BE_SOC_DEV; k++) {
csi2_be_soc = &isys->csi2_be_soc[k];
rval =
}
}
- for (i = 0; i < tpg->ntpgs; i++) {
- rval = media_create_pad_link(&isys->tpg[i].asd.sd.entity,
- TPG_PAD_SOURCE,
- &isys->csi2_be.asd.sd.entity,
- CSI2_BE_PAD_SINK, 0);
- if (rval) {
- dev_info(&isys->adev->dev,
- "can't create link between tpg and csi2_be\n");
- goto fail;
- }
-
- for (k = 0; k < NR_OF_CSI2_BE_SOC_DEV; k++) {
- csi2_be_soc = &isys->csi2_be_soc[k];
- rval =
- media_create_pad_link(&isys->tpg[i].asd.sd.entity,
- TPG_PAD_SOURCE,
- &csi2_be_soc->asd.sd.entity,
- CSI2_BE_SOC_PAD_SINK, 0);
- if (rval) {
- dev_info(&isys->adev->dev,
- "can't create link tpg->be_soc\n");
- goto fail;
- }
- }
- }
-
return 0;
fail:
if (pipe->csi2)
ipu_isys_csi2_sof_event(pipe->csi2);
-#ifdef IPU_TPG_FRAME_SYNC
- if (pipe->tpg)
- ipu_isys_tpg_sof_event(pipe->tpg);
-#endif
pipe->seq[pipe->seq_index].sequence =
atomic_read(&pipe->sequence) - 1;
pipe->seq[pipe->seq_index].timestamp = ts;
if (pipe->csi2)
ipu_isys_csi2_eof_event(pipe->csi2);
-#ifdef IPU_TPG_FRAME_SYNC
- if (pipe->tpg)
- ipu_isys_tpg_eof_event(pipe->tpg);
-#endif
-
dev_dbg(&adev->dev,
"eof: handle %d: (index %u), timestamp 0x%16.16llx\n",
resp->stream_handle,
#include "ipu-isys-media.h"
#include "ipu-isys-csi2.h"
#include "ipu-isys-csi2-be.h"
-#include "ipu-isys-tpg.h"
#include "ipu-isys-video.h"
#include "ipu-pdata.h"
#include "ipu-fw-isys.h"
#define IPU_ISYS_MAX_WIDTH 16384U
#define IPU_ISYS_MAX_HEIGHT 16384U
-#define NR_OF_CSI2_BE_SOC_DEV 8
+#define NR_OF_CSI2_BE_SOC_DEV 1
/* the threshold granularity is 2KB on IPU6 */
#define IPU6_SRAM_GRANULRITY_SHIFT 11
* @lib_mutex: optional external library mutex
* @pdata: platform data pointer
* @csi2: CSI-2 receivers
- * @tpg: test pattern generators
* @csi2_be: CSI-2 back-ends
* @fw: ISYS firmware binary (unsecure firmware)
* @fw_sgt: fw scatterlist
struct ipu_isys_pdata *pdata;
struct ipu_isys_csi2 *csi2;
- struct ipu_isys_tpg *tpg;
struct ipu_isys_csi2_be csi2_be;
struct ipu_isys_csi2_be_soc csi2_be_soc[NR_OF_CSI2_BE_SOC_DEV];
const struct firmware *fw;
unsigned int *offsets;
};
-struct ipu_isys_internal_tpg_pdata {
- unsigned int ntpgs;
- unsigned int *offsets;
- unsigned int *sels;
-};
-
/*
* One place to handle all the IPU HW variations
*/
struct ipu_isys_internal_pdata {
struct ipu_isys_internal_csi2_pdata csi2;
- struct ipu_isys_internal_tpg_pdata tpg;
struct ipu_hw_variants hw_variant;
u32 num_parallel_streams;
u32 isys_dma_overshoot;
ipu6-isys-csi2.o \
ipu6-isys-gpc.o \
../ipu-isys-csi2-be-soc.o \
- ../ipu-isys-csi2-be.o \
../ipu-fw-isys.o \
../ipu-isys-video.o \
../ipu-isys-queue.o \
../ipu-isys-subdev.o
-intel-ipu6-isys-objs += ../ipu-isys-tpg.o
-
obj-$(CONFIG_VIDEO_INTEL_IPU6) += intel-ipu6-isys.o
intel-ipu6-psys-objs += ../ipu-psys.o \
#include "ipu-platform-regs.h"
#include "ipu-trace.h"
#include "ipu-isys.h"
-#include "ipu-isys-tpg.h"
#include "ipu-platform-isys-csi2-reg.h"
const struct ipu_isys_pixelformat ipu_isys_pfmts[] = {
return IRQ_HANDLED;
}
-void ipu_isys_tpg_sof_event(struct ipu_isys_tpg *tpg)
-{
- struct ipu_isys_pipeline *ip = NULL;
- struct v4l2_event ev = {
- .type = V4L2_EVENT_FRAME_SYNC,
- };
- struct video_device *vdev = tpg->asd.sd.devnode;
- unsigned long flags;
- unsigned int i, nr;
-
- nr = (ipu_ver == IPU_VER_6 || ipu_ver == IPU_VER_6EP) ?
- IPU6_ISYS_CSI_PORT_NUM : IPU6SE_ISYS_CSI_PORT_NUM;
-
- spin_lock_irqsave(&tpg->isys->lock, flags);
- for (i = 0; i < nr; i++) {
- if (tpg->isys->pipes[i] && tpg->isys->pipes[i]->tpg == tpg) {
- ip = tpg->isys->pipes[i];
- break;
- }
- }
-
- /* Pipe already vanished */
- if (!ip) {
- spin_unlock_irqrestore(&tpg->isys->lock, flags);
- return;
- }
-
- ev.u.frame_sync.frame_sequence =
- atomic_inc_return(&ip->sequence) - 1;
- spin_unlock_irqrestore(&tpg->isys->lock, flags);
-
- v4l2_event_queue(vdev, &ev);
-
- dev_dbg(&tpg->isys->adev->dev,
- "sof_event::tpg-%i sequence: %i\n",
- tpg->index, ev.u.frame_sync.frame_sequence);
-}
-
-void ipu_isys_tpg_eof_event(struct ipu_isys_tpg *tpg)
-{
- struct ipu_isys_pipeline *ip = NULL;
- unsigned long flags;
- unsigned int i, nr;
- u32 frame_sequence;
-
- nr = (ipu_ver == IPU_VER_6 || ipu_ver == IPU_VER_6EP) ?
- IPU6_ISYS_CSI_PORT_NUM : IPU6SE_ISYS_CSI_PORT_NUM;
-
- spin_lock_irqsave(&tpg->isys->lock, flags);
- for (i = 0; i < nr; i++) {
- if (tpg->isys->pipes[i] && tpg->isys->pipes[i]->tpg == tpg) {
- ip = tpg->isys->pipes[i];
- break;
- }
- }
-
- /* Pipe already vanished */
- if (!ip) {
- spin_unlock_irqrestore(&tpg->isys->lock, flags);
- return;
- }
-
- frame_sequence = atomic_read(&ip->sequence);
-
- spin_unlock_irqrestore(&tpg->isys->lock, flags);
-
- dev_dbg(&tpg->isys->adev->dev,
- "eof_event::tpg-%i sequence: %i\n",
- tpg->index, frame_sequence);
-}
-
-int tpg_set_stream(struct v4l2_subdev *sd, int enable)
-{
- struct ipu_isys_tpg *tpg = to_ipu_isys_tpg(sd);
- __u32 code = tpg->asd.ffmt[TPG_PAD_SOURCE].code;
- unsigned int bpp = ipu_isys_mbus_code_to_bpp(code);
- struct ipu_isys_pipeline *ip =
- to_ipu_isys_pipeline(sd->entity.pipe);
-
- /*
- * MIPI_GEN block is CSI2 FB. Need to enable/disable TPG selection
- * register to control the TPG streaming.
- */
- if (tpg->sel)
- writel(enable ? 1 : 0, tpg->sel);
-
- if (!enable) {
- ip->tpg = NULL;
- writel(0, tpg->base +
- CSI_REG_CSI_FE_ENABLE -
- CSI_REG_PIXGEN_COM_BASE_OFFSET);
- writel(CSI_SENSOR_INPUT, tpg->base +
- CSI_REG_CSI_FE_MUX_CTRL -
- CSI_REG_PIXGEN_COM_BASE_OFFSET);
- writel(CSI_CNTR_SENSOR_LINE_ID |
- CSI_CNTR_SENSOR_FRAME_ID,
- tpg->base + CSI_REG_CSI_FE_SYNC_CNTR_SEL -
- CSI_REG_PIXGEN_COM_BASE_OFFSET);
- writel(0, tpg->base + MIPI_GEN_REG_COM_ENABLE);
- return 0;
- }
-
- ip->has_sof = true;
- ip->tpg = tpg;
- /* Select MIPI GEN as input */
- writel(0, tpg->base + CSI_REG_CSI_FE_MODE -
- CSI_REG_PIXGEN_COM_BASE_OFFSET);
- writel(1, tpg->base + CSI_REG_CSI_FE_ENABLE -
- CSI_REG_PIXGEN_COM_BASE_OFFSET);
- writel(CSI_MIPIGEN_INPUT, tpg->base +
- CSI_REG_CSI_FE_MUX_CTRL - CSI_REG_PIXGEN_COM_BASE_OFFSET);
- writel(0, tpg->base + CSI_REG_CSI_FE_SYNC_CNTR_SEL -
- CSI_REG_PIXGEN_COM_BASE_OFFSET);
-
- writel(MIPI_GEN_COM_DTYPE_RAW(bpp),
- tpg->base + MIPI_GEN_REG_COM_DTYPE);
- writel(ipu_isys_mbus_code_to_mipi(code),
- tpg->base + MIPI_GEN_REG_COM_VTYPE);
- writel(0, tpg->base + MIPI_GEN_REG_COM_VCHAN);
-
- writel(0, tpg->base + MIPI_GEN_REG_SYNG_NOF_FRAMES);
-
- writel(DIV_ROUND_UP(tpg->asd.ffmt[TPG_PAD_SOURCE].width *
- bpp, BITS_PER_BYTE),
- tpg->base + MIPI_GEN_REG_COM_WCOUNT);
- writel(DIV_ROUND_UP(tpg->asd.ffmt[TPG_PAD_SOURCE].width,
- MIPI_GEN_PPC),
- tpg->base + MIPI_GEN_REG_SYNG_NOF_PIXELS);
- writel(tpg->asd.ffmt[TPG_PAD_SOURCE].height,
- tpg->base + MIPI_GEN_REG_SYNG_NOF_LINES);
-
- writel(0, tpg->base + MIPI_GEN_REG_TPG_MODE);
- writel(-1, tpg->base + MIPI_GEN_REG_TPG_HCNT_MASK);
- writel(-1, tpg->base + MIPI_GEN_REG_TPG_VCNT_MASK);
- writel(-1, tpg->base + MIPI_GEN_REG_TPG_XYCNT_MASK);
- writel(0, tpg->base + MIPI_GEN_REG_TPG_HCNT_DELTA);
- writel(0, tpg->base + MIPI_GEN_REG_TPG_VCNT_DELTA);
-
- v4l2_ctrl_handler_setup(&tpg->asd.ctrl_handler);
-
- writel(2, tpg->base + MIPI_GEN_REG_COM_ENABLE);
- return 0;
-}
// SPDX-License-Identifier: GPL-2.0
-// Copyright (C) 2020 Intel Corporation
+// Copyright (C) 2018 - 2021 Intel Corporation
#include <linux/device.h>
#include <linux/delay.h>
IPU_CSI_PORT_D_ADDR_OFFSET,
};
-static unsigned int ipu6se_tpg_offsets[] = {
- IPU_CSI_PORT_A_PIXGEN_ADDR_OFFSET,
- IPU_CSI_PORT_B_PIXGEN_ADDR_OFFSET,
- IPU_CSI_PORT_C_PIXGEN_ADDR_OFFSET,
- IPU_CSI_PORT_D_PIXGEN_ADDR_OFFSET,
-};
-
-static unsigned int ipu6_tpg_offsets[] = {
- IPU_CSI_PORT_A_PIXGEN_ADDR_OFFSET,
- IPU_CSI_PORT_B_PIXGEN_ADDR_OFFSET,
- IPU_CSI_PORT_C_PIXGEN_ADDR_OFFSET,
- IPU_CSI_PORT_D_PIXGEN_ADDR_OFFSET,
- IPU_CSI_PORT_E_PIXGEN_ADDR_OFFSET,
- IPU_CSI_PORT_F_PIXGEN_ADDR_OFFSET,
- IPU_CSI_PORT_G_PIXGEN_ADDR_OFFSET,
- IPU_CSI_PORT_H_PIXGEN_ADDR_OFFSET
-};
-
static unsigned int ipu6_csi_offsets[] = {
IPU_CSI_PORT_A_ADDR_OFFSET,
IPU_CSI_PORT_B_ADDR_OFFSET,
if (ipu_ver == IPU_VER_6 || ipu_ver == IPU_VER_6EP) {
isys_ipdata.csi2.nports = ARRAY_SIZE(ipu6_csi_offsets);
isys_ipdata.csi2.offsets = ipu6_csi_offsets;
- isys_ipdata.tpg.ntpgs = ARRAY_SIZE(ipu6_tpg_offsets);
- isys_ipdata.tpg.offsets = ipu6_tpg_offsets;
- isys_ipdata.tpg.sels = NULL;
isys_ipdata.num_parallel_streams = IPU6_ISYS_NUM_STREAMS;
psys_ipdata.hw_variant.spc_offset = IPU6_PSYS_SPC_OFFSET;
} else if (ipu_ver == IPU_VER_6SE) {
isys_ipdata.csi2.nports = ARRAY_SIZE(ipu6se_csi_offsets);
isys_ipdata.csi2.offsets = ipu6se_csi_offsets;
- isys_ipdata.tpg.ntpgs = ARRAY_SIZE(ipu6se_tpg_offsets);
- isys_ipdata.tpg.offsets = ipu6se_tpg_offsets;
- isys_ipdata.tpg.sels = NULL;
isys_ipdata.num_parallel_streams = IPU6SE_ISYS_NUM_STREAMS;
psys_ipdata.hw_variant.spc_offset = IPU6SE_PSYS_SPC_OFFSET;
}
projects / mirror_ubuntu-jammy-kernel.git / commitdiff