}
-void resource_unreference_clock_source(
+bool resource_unreference_clock_source(
struct resource_context *res_ctx,
const struct resource_pool *pool,
- struct clock_source **clock_source)
+ struct clock_source *clock_source)
{
int i;
+ bool need_reset = false;
+
for (i = 0; i < pool->clk_src_count; i++) {
- if (pool->clock_sources[i] != *clock_source)
+ if (pool->clock_sources[i] != clock_source)
continue;
res_ctx->clock_source_ref_count[i]--;
if (res_ctx->clock_source_ref_count[i] == 0)
- (*clock_source)->funcs->cs_power_down(*clock_source);
+ need_reset = true;
break;
}
- if (pool->dp_clock_source == *clock_source) {
+ if (pool->dp_clock_source == clock_source) {
res_ctx->dp_clock_source_ref_count--;
if (res_ctx->dp_clock_source_ref_count == 0)
- (*clock_source)->funcs->cs_power_down(*clock_source);
+ need_reset = true;
}
- *clock_source = NULL;
+
+ return need_reset;
}
void resource_reference_clock_source(
if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
!find_pll_sharable_stream(stream, new_ctx)) {
- resource_unreference_clock_source(
+ if (resource_unreference_clock_source(
&new_ctx->res_ctx,
dc->res_pool,
- &pipe_ctx->clock_source);
+ pipe_ctx->clock_source)) {
+ pipe_ctx->clock_source->funcs->cs_power_down(pipe_ctx->clock_source);
+ pipe_ctx->clock_source = NULL;
+ }
+
pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
resource_reference_clock_source(
&new_ctx->res_ctx,
if (clk_src &&
clk_src != pipe_ctx->clock_source) {
- resource_unreference_clock_source(
- res_ctx, dc->res_pool,
- &pipe_ctx->clock_source);
+ if (resource_unreference_clock_source(res_ctx,
+ dc->res_pool, pipe_ctx->clock_source)) {
+ pipe_ctx->clock_source->funcs->cs_power_down(pipe_ctx->clock_source);
+ pipe_ctx->clock_source = NULL;
+ }
+
pipe_ctx->clock_source = clk_src;
resource_reference_clock_source(
res_ctx, dc->res_pool, clk_src);
pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
- resource_unreference_clock_source(
+ if (resource_unreference_clock_source(
&dc->current_state->res_ctx, dc->res_pool,
- &pipe_ctx_old->clock_source);
+ pipe_ctx_old->clock_source)) {
+ pipe_ctx_old->clock_source->funcs->cs_power_down(pipe_ctx_old->clock_source);
+ pipe_ctx_old->clock_source = NULL;
+ }
dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx);
}
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
- resource_unreference_clock_source(
- &context->res_ctx, dc->res_pool,
- &pipe_ctx->clock_source);
+ if (resource_unreference_clock_source(&context->res_ctx,
+ dc->res_pool, pipe_ctx->clock_source)) {
+ pipe_ctx->clock_source->funcs->cs_power_down(pipe_ctx->clock_source);
+ pipe_ctx->clock_source = NULL;
+ }
+
for (i = 0; i < dc->res_pool->pipe_count; i++)
if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
void resource_build_info_frame(struct pipe_ctx *pipe_ctx);
-void resource_unreference_clock_source(
+bool resource_unreference_clock_source(
struct resource_context *res_ctx,
const struct resource_pool *pool,
- struct clock_source **clock_source);
+ struct clock_source *clock_source);
void resource_reference_clock_source(
struct resource_context *res_ctx,