drm/amd/display: Fix incorrect dcn1 bandwidth calculations

[WHY]
Typos cause bandwidth calculation errors, one
of which can cause infinite loop on dcn1 with eDP

Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
index 1ef0074302c5c4eb6c52362df7f2e59e08992310..41284e2633250449fd4b7cb916d6f2bff0d4af1a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
@@ -805,7 +805,7 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v)
 
                                        if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
                                                v->time_for_meta_pte_without_immediate_flip = dcn_bw_max3(
-                                                               v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k],
+                                                               v->meta_pte_bytes_frame[k] / v->prefetch_bw[k],
                                                                v->extra_latency,
                                                                v->htotal[k] / v->pixel_clock[k] / 4.0);
                                        } else {
@@ -814,7 +814,7 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v)
 
                                        if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) {
                                                v->time_for_meta_and_dpte_row_without_immediate_flip = dcn_bw_max3((
-                                                               v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bandwidth[k],
+                                                               v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bw[k],
                                                                v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip,
                                                                v->extra_latency);
                                        } else {
@@ -827,7 +827,7 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v)
                                        v->lines_for_meta_and_dpte_row_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_and_dpte_row_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
                                        v->maximum_vstartup = v->maximum_vstartup - 1;
 
-                                       if (v->lines_for_meta_pte_without_immediate_flip[k] < 8.0 && v->lines_for_meta_and_dpte_row_without_immediate_flip[k] < 16.0)
+                                       if (v->lines_for_meta_pte_without_immediate_flip[k] < 32.0 && v->lines_for_meta_and_dpte_row_without_immediate_flip[k] < 16.0)
                                                break;
 
                                } while(1);