cpufreq: intel_pstate: ITMT support for overclocked system

BugLink: https://bugs.launchpad.net/bugs/1969857
commit 03c83982a0278207709143ba78c5a470179febee upstream.

On systems with overclocking enabled, CPPC Highest Performance can be
hard coded to 0xff. In this case even if we have cores with different
highest performance, ITMT can't be enabled as the current implementation
depends on CPPC Highest Performance.

On such systems we can use MSR_HWP_CAPABILITIES maximum performance field
when CPPC.Highest Performance is 0xff.

Due to legacy reasons, we can't solely depend on MSR_HWP_CAPABILITIES as
in some older systems CPPC Highest Performance is the only way to identify
different performing cores.

Reported-by: Michael Larabel <Michael@MichaelLarabel.com>
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Tested-by: Michael Larabel <Michael@MichaelLarabel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Dimitri John Ledkov <dimitri.ledkov@canonical.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>

diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
index e15c3bc17a55ce527e511a116ca038c8deea1af2..8a2c6b58b6524fefa42cde227a4538d0ab03c6fe 100644 (file)
--- a/drivers/cpufreq/intel_pstate.c
+++ b/drivers/cpufreq/intel_pstate.c
@@ -335,6 +335,8 @@ static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
 
 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
 
+#define CPPC_MAX_PERF  U8_MAX
+
 static void intel_pstate_set_itmt_prio(int cpu)
 {
        struct cppc_perf_caps cppc_perf;
@@ -345,6 +347,14 @@ static void intel_pstate_set_itmt_prio(int cpu)
        if (ret)
                return;
 
+       /*
+        * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff.
+        * In this case we can't use CPPC.highest_perf to enable ITMT.
+        * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide.
+        */
+       if (cppc_perf.highest_perf == CPPC_MAX_PERF)
+               cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
+
        /*
         * The priorities can be set regardless of whether or not
         * sched_set_itmt_support(true) has been called and it is valid to