static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int i;
qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
static void mips_cpu_set_pc(CPUState *cs, vaddr value)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
-
- mips_env_set_pc(&cpu->env, value);
+ mips_env_set_pc(cpu_env(cs), value);
}
static vaddr mips_cpu_get_pc(CPUState *cs)
static bool mips_cpu_has_work(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
bool has_work = false;
/*
static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
- MIPSCPU *cpu = MIPS_CPU(s);
- CPUMIPSState *env = &cpu->env;
-
- if (!(env->insn_flags & ISA_NANOMIPS32)) {
+ if (!(cpu_env(s)->insn_flags & ISA_NANOMIPS32)) {
#if TARGET_BIG_ENDIAN
info->print_insn = print_insn_big_mips;
#else
int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
if (n < 32) {
return gdb_get_regl(mem_buf, env->active_tc.gpr[n]);
int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
target_ulong tmp;
tmp = ldtul_p(mem_buf);
int kvm_arch_init_vcpu(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int ret = 0;
qemu_add_vm_change_state_handler(kvm_mips_update_state, cs);
*/
static int kvm_mips_save_count(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
uint64_t count_ctl;
int err, ret = 0;
*/
static int kvm_mips_restore_count(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
uint64_t count_ctl;
int err_dc, err, ret = 0;
static int kvm_mips_put_fpu_registers(CPUState *cs, int level)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int err, ret = 0;
unsigned int i;
static int kvm_mips_get_fpu_registers(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int err, ret = 0;
unsigned int i;
static int kvm_mips_put_cp0_registers(CPUState *cs, int level)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int err, ret = 0;
(void)level;
static int kvm_mips_get_cp0_registers(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int err, ret = 0;
err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
int kvm_arch_put_registers(CPUState *cs, int level)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
struct kvm_regs regs;
int ret;
int i;
int kvm_arch_get_registers(CPUState *cs)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int ret = 0;
struct kvm_regs regs;
int i;
hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
hwaddr phys_addr;
int prot;
void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
env->active_tc.PC = tb->pc;
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
int error_code = 0;
int excp;
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
- CPUMIPSState *env = &cpu->env;
+ MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cs);
+ CPUMIPSState *env = cpu_env(cs);
if (access_type == MMU_INST_FETCH) {
do_raise_exception(env, EXCP_IBE, retaddr);
bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
if ((env->hflags & MIPS_HFLAG_BMASK) != 0
&& !(cs->tcg_cflags & CF_PCREL) && env->active_tc.PC != tb->pc) {
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
hwaddr physical;
int prot;
int ret = TLBRET_BADADDR;
bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
if (cpu_mips_hw_interrupts_enabled(env) &&
cpu_mips_hw_interrupts_pending(env)) {
const TranslationBlock *tb,
const uint64_t *data)
{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
+ CPUMIPSState *env = cpu_env(cs);
env->active_tc.PC = data[0];
env->hflags &= ~MIPS_HFLAG_BMASK;