dt-bindings: clock: Add license and reformat Exynos5410 clock IDs

Add license and copyrights (file introduced in 2014) to header with
Exynos5410 clock IDs. Additionally reformat it to improve readability.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
index 9b180f032e2db394b817702c3a0264eaccca5a96..213f19e0287051f90e3d324a404c378532a86a33 100644 (file)
--- a/include/dt-bindings/clock/exynos5410.h
+++ b/include/dt-bindings/clock/exynos5410.h
@@ -1,33 +1,43 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Exynos5421 clock controller.
+*/
+
 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
 #define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
 
 /* core clocks */
-#define CLK_FIN_PLL 1
-#define CLK_FOUT_APLL 2
-#define CLK_FOUT_CPLL 3
-#define CLK_FOUT_MPLL 4
-#define CLK_FOUT_BPLL 5
-#define CLK_FOUT_KPLL 6
+#define CLK_FIN_PLL            1
+#define CLK_FOUT_APLL          2
+#define CLK_FOUT_CPLL          3
+#define CLK_FOUT_MPLL          4
+#define CLK_FOUT_BPLL          5
+#define CLK_FOUT_KPLL          6
 
 /* gate for special clocks (sclk) */
-#define CLK_SCLK_UART0 128
-#define CLK_SCLK_UART1 129
-#define CLK_SCLK_UART2 130
-#define CLK_SCLK_UART3 131
-#define CLK_SCLK_MMC0 132
-#define CLK_SCLK_MMC1 133
-#define CLK_SCLK_MMC2 134
+#define CLK_SCLK_UART0         128
+#define CLK_SCLK_UART1         129
+#define CLK_SCLK_UART2         130
+#define CLK_SCLK_UART3         131
+#define CLK_SCLK_MMC0          132
+#define CLK_SCLK_MMC1          133
+#define CLK_SCLK_MMC2          134
 
 /* gate clocks */
-#define CLK_UART0 257
-#define CLK_UART1 258
-#define CLK_UART2 259
-#define CLK_UART3 260
-#define CLK_MCT 315
-#define CLK_MMC0 351
-#define CLK_MMC1 352
-#define CLK_MMC2 353
+#define CLK_UART0              257
+#define CLK_UART1              258
+#define CLK_UART2              259
+#define CLK_UART3              260
+#define CLK_MCT                        315
+#define CLK_MMC0               351
+#define CLK_MMC1               352
+#define CLK_MMC2               353
 
-#define CLK_NR_CLKS 512
+#define CLK_NR_CLKS            512
 
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */