target/riscv: Add checks for several RVC reserved operands

C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved
operands that were not diagnosed.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
index 055859d29f6155da63cff3333b8bac7a89f733d9..672e1e916f6bd213949642819141fa20bd2870a7 100644 (file)
--- a/target/riscv/insn16-64.decode
+++ b/target/riscv/insn16-64.decode
@@ -21,10 +21,16 @@ ld                011  ... ... .. ... 00 @cl_d
 sd                111  ... ... .. ... 00 @cs_d
 
 # *** RV64C Standard Extension (Quadrant 1) ***
-addiw             001 .  .....  ..... 01 @ci
+{
+  illegal         001 -  00000  ----- 01 # c.addiw, RES rd=0
+  addiw           001 .  .....  ..... 01 @ci
+}
 subw              100 1 11 ... 00 ... 01 @cs_2
 addw              100 1 11 ... 01 ... 01 @cs_2
 
 # *** RV64C Standard Extension (Quadrant 2) ***
-ld                011 .  .....  ..... 10 @c_ldsp
+{
+  illegal         011 -  00000  ----- 10 # c.ldsp, RES rd=0
+  ld              011 .  .....  ..... 10 @c_ldsp
+}
 sd                111 .  .....  ..... 10 @c_sdsp

diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 433c0e8c6861c13207f0913144ad1cfbe17637a6..1cb93876fe0fc839277623641dcab6154d208065 100644 (file)
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -96,6 +96,7 @@ sw                110  ... ... .. ... 00 @cs_w
 addi              000 .  .....  ..... 01 @ci
 addi              010 .  .....  ..... 01 @c_li
 {
+  illegal         011 0  -----  00000 01 # c.addi16sp and c.lui, RES nzimm=0
   addi            011 .  00010  ..... 01 @c_addi16sp
   lui             011 .  .....  ..... 01 @c_lui
 }
@@ -113,8 +114,12 @@ bne               111  ... ...  ..... 01 @cb_z
 # *** RV32/64C Standard Extension (Quadrant 2) ***
 slli              000 .  .....  ..... 10 @c_shift2
 fld               001 .  .....  ..... 10 @c_ldsp
-lw                010 .  .....  ..... 10 @c_lwsp
 {
+  illegal         010 -  00000  ----- 10 # c.lwsp, RES rd=0
+  lw              010 .  .....  ..... 10 @c_lwsp
+}
+{
+  illegal         100 0  00000  00000 10 # c.jr, RES rs1=0
   jalr            100 0  .....  00000 10 @c_jalr rd=0  # C.JR
   addi            100 0  .....  ..... 10 @c_mv
 }