return 0;
default:
cpu_abort (cpu_single_env,
- "integratorcm_read: Unimplemented offset 0x%x\n", offset);
+ "integratorcm_read: Unimplemented offset 0x%x\n", (int)offset);
return 0;
}
}
break;
default:
cpu_abort (cpu_single_env,
- "integratorcm_write: Unimplemented offset 0x%x\n", offset);
+ "integratorcm_write: Unimplemented offset 0x%x\n", (int)offset);
break;
}
}
case 3: /* CP_DECODE */
return 0x11;
default:
- cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n", offset);
+ cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n",
+ (int)offset);
return 0;
}
}
/* Nothing interesting implemented yet. */
break;
default:
- cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n", offset);
+ cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n",
+ (int)offset);
}
}
static CPUReadMemoryFunc *icp_control_readfn[] = {
case 18: /* UARTDMACR */
return s->dmacr;
default:
- cpu_abort (cpu_single_env, "pl011_read: Bad offset %x\n", offset);
+ cpu_abort (cpu_single_env, "pl011_read: Bad offset %x\n", (int)offset);
return 0;
}
}
cpu_abort(cpu_single_env, "PL011: DMA not implemented\n");
break;
default:
- cpu_abort (cpu_single_env, "pl011_write: Bad offset %x\n", offset);
+ cpu_abort (cpu_single_env, "pl011_write: Bad offset %x\n", (int)offset);
}
}
case 4: /* KMIIR */
return s->pending | 2;
default:
- cpu_abort (cpu_single_env, "pl050_read: Bad offset %x\n", offset);
+ cpu_abort (cpu_single_env, "pl050_read: Bad offset %x\n", (int)offset);
return 0;
}
}
s->clk = value;
return;
default:
- cpu_abort (cpu_single_env, "pl050_write: Bad offset %x\n", offset);
+ cpu_abort (cpu_single_env, "pl050_write: Bad offset %x\n", (int)offset);
}
}
static CPUReadMemoryFunc *pl050_readfn[] = {
return s->sync;
default:
bad_offset:
- cpu_abort(cpu_single_env, "pl080_read: Bad offset %x\n", offset);
+ cpu_abort(cpu_single_env, "pl080_read: Bad offset %x\n", (int)offset);
return 0;
}
}
break;
default:
bad_offset:
- cpu_abort(cpu_single_env, "pl080_write: Bad offset %x\n", offset);
+ cpu_abort(cpu_single_env, "pl080_write: Bad offset %x\n", (int)offset);
}
pl080_update(s);
}
case 12: /* LCDLPCURR */
return s->lpbase;
default:
- cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", offset);
+ cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", (int)offset);
return 0;
}
}
pl110_update(s);
break;
default:
- cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", offset);
+ cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", (int)offset);
}
}
return value;
}
default:
- cpu_abort (cpu_single_env, "pl181_read: Bad offset %x\n", offset);
+ cpu_abort (cpu_single_env, "pl181_read: Bad offset %x\n", (int)offset);
return 0;
}
}
}
break;
default:
- cpu_abort (cpu_single_env, "pl181_write: Bad offset %x\n", offset);
+ cpu_abort (cpu_single_env, "pl181_write: Bad offset %x\n", (int)offset);
}
pl181_update(s);
}
case 13: /* DEFVECTADDR */
return s->vect_addr[16];
default:
- cpu_abort (cpu_single_env, "pl190_read: Bad offset %x\n", offset);
+ cpu_abort (cpu_single_env, "pl190_read: Bad offset %x\n", (int)offset);
return 0;
}
}
cpu_abort(cpu_single_env, "pl190: Test mode not implemented\n");
break;
default:
- cpu_abort(cpu_single_env, "pl190_write: Bad offset %x\n", offset);
+ cpu_abort(cpu_single_env, "pl190_write: Bad offset %x\n", (int)offset);
return;
}
pl190_update(s);
break;
}
cpu_abort (cpu_single_env, "smc91c111_write: Bad reg %d:%x\n",
- s->bank, offset);
+ s->bank, (int)offset);
}
static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset)
break;
}
cpu_abort (cpu_single_env, "smc91c111_read: Bad reg %d:%x\n",
- s->bank, offset);
+ s->bank, (int)offset);
return 0;
}