#define TCG_TMP2 TCG_REG_T8
#define TCG_TMP3 TCG_REG_T7
+#ifndef CONFIG_SOFTMMU
+#define TCG_GUEST_BASE_REG TCG_REG_S1
+#endif
+
/* check if we really need so many registers :P */
static const int tcg_target_reg_alloc_order[] = {
/* Call saved registers. */
} else if (guest_base == (int16_t)guest_base) {
tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
} else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, guest_base);
- tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP0, addr_regl);
+ tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
}
tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
#endif
} else if (guest_base == (int16_t)guest_base) {
tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
} else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, guest_base);
- tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP0, addr_regl);
+ tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
}
tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
#endif
TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
}
+#ifndef CONFIG_SOFTMMU
+ if (guest_base) {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
+ tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
+ }
+#endif
+
/* Call generated code */
tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
/* delay slot */