drm/i915/icl: Introduce new macros to get combophy registers

combo-phy register instances are at same offset from base for each
combo-phy port, i.e.

Port A base offset: 0x16200
Port B base offset: 0x6C000

All the other addresses for both ports can be derived by calculating
offset to these base addresses.

PORT_CL_DW_OFFSET	0x0
PORT_CL_DW<x>		0 + x * 4

PORT_COMP_OFFSET	0x100
PORT_COMP_DW<x>		0x100 + x * 4

PORT_PCS_AUX_OFFSET     0x300
PORT_PCS_GRP_OFFSET     0x600
PORT_PCS_LN<y>_OFFSET   0x800 + y * 0x100

PORT_TX_AUX_OFFSET      0x380
PORT_TX_GRP_OFFSET      0x680
PORT_TX_LN<y>_OFFSET    0x880 + y * 0x100

And inside each PORT_TX_[AUX|GRP|LN] we add `dw * 4`.

Based on original patch by Mahesh Kumar <mahesh1.kumar@intel.com>.

v2: make port, dw and ln arguments follow the order in
    register's name

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181016023517.8576-1-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ef0c5bc317ddd8f4c67e60a42ebbba966425519f..fa8b52743bd9a1e27dd76e5ec33dbad5ec9572e3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1658,20 +1658,21 @@ enum i915_power_well_id {
 /*
  * CNL/ICL Port/COMBO-PHY Registers
  */
+#define _ICL_COMBOPHY_A                        0x162000
+#define _ICL_COMBOPHY_B                        0x6C000
+#define _ICL_COMBOPHY(port)            _PICK(port, _ICL_COMBOPHY_A, \
+                                             _ICL_COMBOPHY_B)
+
 /* CNL/ICL Port CL_DW registers */
-#define CNL_PORT_CL1CM_DW5     _MMIO(0x162014)
-#define _ICL_PORT_CL_DW5_A     0x162014
-#define _ICL_PORT_CL_DW5_B     0x6C014
-#define ICL_PORT_CL_DW5(port)  _MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
-                                                _ICL_PORT_CL_DW5_B)
+#define _ICL_PORT_CL_DW(dw, port)      (_ICL_COMBOPHY(port) + \
+                                        4 * (dw))
+
+#define CNL_PORT_CL1CM_DW5             _MMIO(0x162014)
+#define ICL_PORT_CL_DW5(port)          _MMIO(_ICL_PORT_CL_DW(5, port))
 #define   CL_POWER_DOWN_ENABLE         (1 << 4)
 #define   SUS_CLOCK_CONFIG             (3 << 0)
 
-#define _CNL_PORT_CL_DW10_A            0x162028
-#define _ICL_PORT_CL_DW10_B            0x6c028
-#define ICL_PORT_CL_DW10(port)         _MMIO_PORT(port,        \
-                                                  _CNL_PORT_CL_DW10_A, \
-                                                  _ICL_PORT_CL_DW10_B)
+#define ICL_PORT_CL_DW10(port)         _MMIO(_ICL_PORT_CL_DW(10, port))
 #define  PG_SEQ_DELAY_OVERRIDE_MASK    (3 << 25)
 #define  PG_SEQ_DELAY_OVERRIDE_SHIFT   25
 #define  PG_SEQ_DELAY_OVERRIDE_ENABLE  (1 << 24)
@@ -1687,31 +1688,23 @@ enum i915_power_well_id {
 #define  PWR_DOWN_LN_MASK              (0xf << 4)
 #define  PWR_DOWN_LN_SHIFT             4
 
-#define _ICL_PORT_CL_DW12_A            0x162030
-#define _ICL_PORT_CL_DW12_B            0x6C030
+#define ICL_PORT_CL_DW12(port)         _MMIO(_ICL_PORT_CL_DW(12, port))
 #define   ICL_LANE_ENABLE_AUX          (1 << 0)
-#define ICL_PORT_CL_DW12(port)         _MMIO_PORT((port),              \
-                                                  _ICL_PORT_CL_DW12_A, \
-                                                  _ICL_PORT_CL_DW12_B)
 
 /* CNL/ICL Port COMP_DW registers */
+#define _ICL_PORT_COMP                 0x100
+#define _ICL_PORT_COMP_DW(dw, port)    (_ICL_COMBOPHY(port) + \
+                                        _ICL_PORT_COMP + 4 * (dw))
+
 #define CNL_PORT_COMP_DW0              _MMIO(0x162100)
-#define _ICL_PORT_COMP_DW0_A           0x162100
-#define _ICL_PORT_COMP_DW0_B           0x6C100
-#define ICL_PORT_COMP_DW0(port)                _MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
-                                                        _ICL_PORT_COMP_DW0_B)
+#define ICL_PORT_COMP_DW0(port)                _MMIO(_ICL_PORT_COMP_DW(0, port))
 #define   COMP_INIT                    (1 << 31)
 
 #define CNL_PORT_COMP_DW1              _MMIO(0x162104)
-#define _ICL_PORT_COMP_DW1_A           0x162104
-#define _ICL_PORT_COMP_DW1_B           0x6C104
-#define ICL_PORT_COMP_DW1(port)                _MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
-                                                        _ICL_PORT_COMP_DW1_B)
+#define ICL_PORT_COMP_DW1(port)                _MMIO(_ICL_PORT_COMP_DW(1, port))
+
 #define CNL_PORT_COMP_DW3              _MMIO(0x16210c)
-#define _ICL_PORT_COMP_DW3_A           0x16210C
-#define _ICL_PORT_COMP_DW3_B           0x6C10C
-#define ICL_PORT_COMP_DW3(port)                _MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
-                                                        _ICL_PORT_COMP_DW3_B)
+#define ICL_PORT_COMP_DW3(port)                _MMIO(_ICL_PORT_COMP_DW(3, port))
 #define   PROCESS_INFO_DOT_0           (0 << 26)
 #define   PROCESS_INFO_DOT_1           (1 << 26)
 #define   PROCESS_INFO_DOT_4           (2 << 26)
@@ -1724,17 +1717,10 @@ enum i915_power_well_id {
 #define   VOLTAGE_INFO_SHIFT           24
 
 #define CNL_PORT_COMP_DW9              _MMIO(0x162124)
-#define _ICL_PORT_COMP_DW9_A           0x162124
-#define _ICL_PORT_COMP_DW9_B           0x6C124
-#define ICL_PORT_COMP_DW9(port)                _MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
-                                                        _ICL_PORT_COMP_DW9_B)
+#define ICL_PORT_COMP_DW9(port)                _MMIO(_ICL_PORT_COMP_DW(9, port))
 
 #define CNL_PORT_COMP_DW10             _MMIO(0x162128)
-#define _ICL_PORT_COMP_DW10_A          0x162128
-#define _ICL_PORT_COMP_DW10_B          0x6C128
-#define ICL_PORT_COMP_DW10(port)       _MMIO_PORT(port, \
-                                                  _ICL_PORT_COMP_DW10_A, \
-                                                  _ICL_PORT_COMP_DW10_B)
+#define ICL_PORT_COMP_DW10(port)       _MMIO(_ICL_PORT_COMP_DW(10, port))
 
 /* CNL/ICL Port PCS registers */
 #define _CNL_PORT_PCS_DW1_GRP_AE       0x162304
@@ -1754,7 +1740,6 @@ enum i915_power_well_id {
                                                    _CNL_PORT_PCS_DW1_GRP_D, \
                                                    _CNL_PORT_PCS_DW1_GRP_AE, \
                                                    _CNL_PORT_PCS_DW1_GRP_F))
-
 #define CNL_PORT_PCS_DW1_LN0(port)     _MMIO(_PICK(port, \
                                                    _CNL_PORT_PCS_DW1_LN0_AE, \
                                                    _CNL_PORT_PCS_DW1_LN0_B, \
@@ -1763,21 +1748,18 @@ enum i915_power_well_id {
                                                    _CNL_PORT_PCS_DW1_LN0_AE, \
                                                    _CNL_PORT_PCS_DW1_LN0_F))
 
-#define _ICL_PORT_PCS_DW1_GRP_A                0x162604
-#define _ICL_PORT_PCS_DW1_GRP_B                0x6C604
-#define _ICL_PORT_PCS_DW1_LN0_A                0x162804
-#define _ICL_PORT_PCS_DW1_LN0_B                0x6C804
-#define _ICL_PORT_PCS_DW1_AUX_A                0x162304
-#define _ICL_PORT_PCS_DW1_AUX_B                0x6c304
-#define ICL_PORT_PCS_DW1_GRP(port)     _MMIO_PORT(port,\
-                                                  _ICL_PORT_PCS_DW1_GRP_A, \
-                                                  _ICL_PORT_PCS_DW1_GRP_B)
-#define ICL_PORT_PCS_DW1_LN0(port)     _MMIO_PORT(port, \
-                                                  _ICL_PORT_PCS_DW1_LN0_A, \
-                                                  _ICL_PORT_PCS_DW1_LN0_B)
-#define ICL_PORT_PCS_DW1_AUX(port)     _MMIO_PORT(port, \
-                                                  _ICL_PORT_PCS_DW1_AUX_A, \
-                                                  _ICL_PORT_PCS_DW1_AUX_B)
+#define _ICL_PORT_PCS_AUX              0x300
+#define _ICL_PORT_PCS_GRP              0x600
+#define _ICL_PORT_PCS_LN(ln)           (0x800 + (ln) * 0x100)
+#define _ICL_PORT_PCS_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \
+                                        _ICL_PORT_PCS_AUX + 4 * (dw))
+#define _ICL_PORT_PCS_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \
+                                        _ICL_PORT_PCS_GRP + 4 * (dw))
+#define _ICL_PORT_PCS_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
+                                         _ICL_PORT_PCS_LN(ln) + 4 * (dw))
+#define ICL_PORT_PCS_DW1_AUX(port)     _MMIO(_ICL_PORT_PCS_DW_AUX(1, port))
+#define ICL_PORT_PCS_DW1_GRP(port)     _MMIO(_ICL_PORT_PCS_DW_GRP(1, port))
+#define ICL_PORT_PCS_DW1_LN0(port)     _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port))
 #define   COMMON_KEEPER_EN             (1 << 26)
 
 /* CNL/ICL Port TX registers */
@@ -1808,23 +1790,22 @@ enum i915_power_well_id {
                                               _CNL_PORT_TX_F_LN0_OFFSET) + \
                                               4 * (dw))
 
-#define CNL_PORT_TX_DW2_GRP(port)      _MMIO(_CNL_PORT_TX_DW_GRP((port), 2))
-#define CNL_PORT_TX_DW2_LN0(port)      _MMIO(_CNL_PORT_TX_DW_LN0((port), 2))
-#define _ICL_PORT_TX_DW2_GRP_A         0x162688
-#define _ICL_PORT_TX_DW2_GRP_B         0x6C688
-#define _ICL_PORT_TX_DW2_LN0_A         0x162888
-#define _ICL_PORT_TX_DW2_LN0_B         0x6C888
-#define _ICL_PORT_TX_DW2_AUX_A         0x162388
-#define _ICL_PORT_TX_DW2_AUX_B         0x6c388
-#define ICL_PORT_TX_DW2_GRP(port)      _MMIO_PORT(port, \
-                                                  _ICL_PORT_TX_DW2_GRP_A, \
-                                                  _ICL_PORT_TX_DW2_GRP_B)
-#define ICL_PORT_TX_DW2_LN0(port)      _MMIO_PORT(port, \
-                                                  _ICL_PORT_TX_DW2_LN0_A, \
-                                                  _ICL_PORT_TX_DW2_LN0_B)
-#define ICL_PORT_TX_DW2_AUX(port)      _MMIO_PORT(port, \
-                                                  _ICL_PORT_TX_DW2_AUX_A, \
-                                                  _ICL_PORT_TX_DW2_AUX_B)
+#define _ICL_PORT_TX_AUX               0x380
+#define _ICL_PORT_TX_GRP               0x680
+#define _ICL_PORT_TX_LN(ln)            (0x880 + (ln) * 0x100)
+
+#define _ICL_PORT_TX_DW_AUX(dw, port)  (_ICL_COMBOPHY(port) + \
+                                        _ICL_PORT_TX_AUX + 4 * (dw))
+#define _ICL_PORT_TX_DW_GRP(dw, port)  (_ICL_COMBOPHY(port) + \
+                                        _ICL_PORT_TX_GRP + 4 * (dw))
+#define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
+                                         _ICL_PORT_TX_LN(ln) + 4 * (dw))
+
+#define CNL_PORT_TX_DW2_GRP(port)      _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
+#define CNL_PORT_TX_DW2_LN0(port)      _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
+#define ICL_PORT_TX_DW2_AUX(port)      _MMIO(_ICL_PORT_TX_DW_AUX(2, port))
+#define ICL_PORT_TX_DW2_GRP(port)      _MMIO(_ICL_PORT_TX_DW_GRP(2, port))
+#define ICL_PORT_TX_DW2_LN0(port)      _MMIO(_ICL_PORT_TX_DW_LN(2, 0, port))
 #define   SWING_SEL_UPPER(x)           (((x) >> 3) << 15)
 #define   SWING_SEL_UPPER_MASK         (1 << 15)
 #define   SWING_SEL_LOWER(x)           (((x) & 0x7) << 11)
@@ -1841,24 +1822,10 @@ enum i915_power_well_id {
 #define CNL_PORT_TX_DW4_LN(port, ln)   _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
                                           ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
                                                    _CNL_PORT_TX_DW4_LN0_AE)))
-#define _ICL_PORT_TX_DW4_GRP_A         0x162690
-#define _ICL_PORT_TX_DW4_GRP_B         0x6C690
-#define _ICL_PORT_TX_DW4_LN0_A         0x162890
-#define _ICL_PORT_TX_DW4_LN1_A         0x162990
-#define _ICL_PORT_TX_DW4_LN0_B         0x6C890
-#define _ICL_PORT_TX_DW4_AUX_A         0x162390
-#define _ICL_PORT_TX_DW4_AUX_B         0x6c390
-#define ICL_PORT_TX_DW4_GRP(port)      _MMIO_PORT(port, \
-                                                  _ICL_PORT_TX_DW4_GRP_A, \
-                                                  _ICL_PORT_TX_DW4_GRP_B)
-#define ICL_PORT_TX_DW4_LN(port, ln)   _MMIO(_PORT(port, \
-                                                  _ICL_PORT_TX_DW4_LN0_A, \
-                                                  _ICL_PORT_TX_DW4_LN0_B) + \
-                                            ((ln) * (_ICL_PORT_TX_DW4_LN1_A - \
-                                                     _ICL_PORT_TX_DW4_LN0_A)))
-#define ICL_PORT_TX_DW4_AUX(port)      _MMIO_PORT(port, \
-                                                  _ICL_PORT_TX_DW4_AUX_A, \
-                                                  _ICL_PORT_TX_DW4_AUX_B)
+#define ICL_PORT_TX_DW4_AUX(port)      _MMIO(_ICL_PORT_TX_DW_AUX(4, port))
+#define ICL_PORT_TX_DW4_GRP(port)      _MMIO(_ICL_PORT_TX_DW_GRP(4, port))
+#define ICL_PORT_TX_DW4_LN0(port)      _MMIO(_ICL_PORT_TX_DW_LN(4, 0, port))
+#define ICL_PORT_TX_DW4_LN(port, ln)   _MMIO(_ICL_PORT_TX_DW_LN(4, ln, port))
 #define   LOADGEN_SELECT               (1 << 31)
 #define   POST_CURSOR_1(x)             ((x) << 12)
 #define   POST_CURSOR_1_MASK           (0x3F << 12)
@@ -1867,23 +1834,11 @@ enum i915_power_well_id {
 #define   CURSOR_COEFF(x)              ((x) << 0)
 #define   CURSOR_COEFF_MASK            (0x3F << 0)
 
-#define CNL_PORT_TX_DW5_GRP(port)      _MMIO(_CNL_PORT_TX_DW_GRP((port), 5))
-#define CNL_PORT_TX_DW5_LN0(port)      _MMIO(_CNL_PORT_TX_DW_LN0((port), 5))
-#define _ICL_PORT_TX_DW5_GRP_A         0x162694
-#define _ICL_PORT_TX_DW5_GRP_B         0x6C694
-#define _ICL_PORT_TX_DW5_LN0_A         0x162894
-#define _ICL_PORT_TX_DW5_LN0_B         0x6C894
-#define _ICL_PORT_TX_DW5_AUX_A         0x162394
-#define _ICL_PORT_TX_DW5_AUX_B         0x6c394
-#define ICL_PORT_TX_DW5_GRP(port)      _MMIO_PORT(port, \
-                                                  _ICL_PORT_TX_DW5_GRP_A, \
-                                                  _ICL_PORT_TX_DW5_GRP_B)
-#define ICL_PORT_TX_DW5_LN0(port)      _MMIO_PORT(port, \
-                                                  _ICL_PORT_TX_DW5_LN0_A, \
-                                                  _ICL_PORT_TX_DW5_LN0_B)
-#define ICL_PORT_TX_DW5_AUX(port)      _MMIO_PORT(port, \
-                                                  _ICL_PORT_TX_DW5_AUX_A, \
-                                                  _ICL_PORT_TX_DW5_AUX_B)
+#define CNL_PORT_TX_DW5_GRP(port)      _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
+#define CNL_PORT_TX_DW5_LN0(port)      _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
+#define ICL_PORT_TX_DW5_AUX(port)      _MMIO(_ICL_PORT_TX_DW_AUX(5, port))
+#define ICL_PORT_TX_DW5_GRP(port)      _MMIO(_ICL_PORT_TX_DW_GRP(5, port))
+#define ICL_PORT_TX_DW5_LN0(port)      _MMIO(_ICL_PORT_TX_DW_LN(5, 0, port))
 #define   TX_TRAINING_EN               (1 << 31)
 #define   TAP2_DISABLE                 (1 << 30)
 #define   TAP3_DISABLE                 (1 << 29)