drm/i915/cnl: Add support slice/subslice/eu configs

Cannonlake Slice and Subslice information has changed.

This patch initially provided by Ben adds the proper sseu
initialization.

v2: This v2 done by Rodrigo includes:
    - Fix on Total slices count by avoiding [1][2] and [2][2].
    - Inclusion of EU Per Subslice.
    - Commit message.
v3: This v3 done by Rodrigo includes:
    - Handle all possible bits and extra fuse register.
    - Use INTEL_GEN macro.
    - Fully assume uniform distribution so remove union
      with eu_per_subslice and add proper the comment.
v4: This v4 done by Rodrigo includes:
    - Consider all bits available: 6 bits for slices [27:22]
      and 4 for subslices [21:18].
v5: This v5 done by Rodrigo includes:
    - sseu->subslice_mask = (1 << 4) - 1 - missed on previous
    versions and noticed by Oscar.

Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170920183525.20530-1-rodrigo.vivi@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 76fd8fda46d240a9008a0e8211a411b30e4bb61e..e4c424ba59051efa03ac59c7a24457b902a76ac2 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2730,6 +2730,11 @@ enum i915_power_well_id {
 #define   GEN9_F2_SS_DIS_SHIFT         20
 #define   GEN9_F2_SS_DIS_MASK          (0xf << GEN9_F2_SS_DIS_SHIFT)
 
+#define   GEN10_F2_S_ENA_SHIFT         22
+#define   GEN10_F2_S_ENA_MASK          (0x3f << GEN10_F2_S_ENA_SHIFT)
+#define   GEN10_F2_SS_DIS_SHIFT                18
+#define   GEN10_F2_SS_DIS_MASK         (0xf << GEN10_F2_SS_DIS_SHIFT)
+
 #define GEN8_EU_DISABLE0               _MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK         0xffffff
 #define   GEN8_EU_DIS0_S1_SHIFT                24
@@ -2745,6 +2750,9 @@ enum i915_power_well_id {
 
 #define GEN9_EU_DISABLE(slice)         _MMIO(0x9134 + (slice)*0x4)
 
+#define GEN10_EU_DISABLE3              _MMIO(0x9140)
+#define   GEN10_EU_DIS_SS_MASK         0xff
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL    _MMIO(0x12050)
 #define   GEN6_BSD_SLEEP_MSG_DISABLE   (1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index fdf9b54b71e9749dbe283cf419eea736ebbc4453..875d428ea75f2b74dabae6e97d30e09676d89930 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -82,6 +82,39 @@ void intel_device_info_dump(struct drm_i915_private *dev_priv)
 #undef PRINT_FLAG
 }
 
+static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+       struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+       const u32 fuse2 = I915_READ(GEN8_FUSE2);
+
+       sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
+                           GEN10_F2_S_ENA_SHIFT;
+       sseu->subslice_mask = (1 << 4) - 1;
+       sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+                                GEN10_F2_SS_DIS_SHIFT);
+
+       sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
+       sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
+       sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
+       sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
+                                    GEN10_EU_DIS_SS_MASK));
+
+       /*
+        * CNL is expected to always have a uniform distribution
+        * of EU across subslices with the exception that any one
+        * EU in any one subslice may be fused off for die
+        * recovery.
+        */
+       sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
+                               DIV_ROUND_UP(sseu->eu_total,
+                                            sseu_subslice_total(sseu)) : 0;
+
+       /* No restrictions on Power Gating */
+       sseu->has_slice_pg = 1;
+       sseu->has_subslice_pg = 1;
+       sseu->has_eu_pg = 1;
+}
+
 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
 {
        struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
@@ -409,8 +442,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
                cherryview_sseu_info_init(dev_priv);
        else if (IS_BROADWELL(dev_priv))
                broadwell_sseu_info_init(dev_priv);
-       else if (INTEL_INFO(dev_priv)->gen >= 9)
+       else if (INTEL_GEN(dev_priv) == 9)
                gen9_sseu_info_init(dev_priv);
+       else if (INTEL_GEN(dev_priv) >= 10)
+               gen10_sseu_info_init(dev_priv);
 
        DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
        DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));