drm/radeon/kms: fix up gart setup on rs600

Set up rs600 gart like r600:
- set gart system aperture to vram
- inside gart system aperture is unmapped*
- outside gart system aperture is mapped*

*mapped refers to memory handled by page tables

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index c4bdfaf9b54cb9e95638bf7ec876d3ad2611b990..11a1da0fc76b575e5e2aaa51fcfdb5e3934d9270 100644 (file)
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -100,40 +100,40 @@ int rs600_gart_enable(struct radeon_device *rdev)
        WREG32(R_00004C_BUS_CNTL, tmp);
        /* FIXME: setup default page */
        WREG32_MC(R_000100_MC_PT0_CNTL,
-                (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
-                 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
+                 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
+                  S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
+
        for (i = 0; i < 19; i++) {
                WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
-                       S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
-                       S_00016C_SYSTEM_ACCESS_MODE_MASK(
-                               V_00016C_SYSTEM_ACCESS_MODE_IN_SYS) |
-                       S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
-                               V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE) |
-                       S_00016C_EFFECTIVE_L1_CACHE_SIZE(1) |
-                       S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
-                       S_00016C_EFFECTIVE_L1_QUEUE_SIZE(1));
+                         S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
+                         S_00016C_SYSTEM_ACCESS_MODE_MASK(
+                                 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
+                         S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
+                                 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
+                         S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
+                         S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
+                         S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
        }
-
-       /* System context map to GART space */
-       WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_start);
-       WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.gtt_end);
-
        /* enable first context */
-       WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
-       WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
        WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
-                       S_000102_ENABLE_PAGE_TABLE(1) |
-                       S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
+                 S_000102_ENABLE_PAGE_TABLE(1) |
+                 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
+
        /* disable all other contexts */
-       for (i = 1; i < 8; i++) {
+       for (i = 1; i < 8; i++)
                WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
-       }
 
        /* setup the page table */
        WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
-                       rdev->gart.table_addr);
+                 rdev->gart.table_addr);
+       WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
+       WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
        WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 
+       /* System context maps to VRAM space */
+       WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
+       WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
+
        /* enable page tables */
        tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
        WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));