- Texas Instruments' LMK04832 Ultra Low-Noise JESD204B Compliant Clock
Jitter Cleaner With Dual Loop PLLs
- Support secure mode of STM32MP1 SoCs
- Improve clock support for Actions S500 SoC
* clk-lmk04832:
clk: lmk04832: Use of match table
clk: lmk04832: Depend on SPI
clk: lmk04832: add support for digital delay
clk: add support for the lmk04832
dt-bindings: clock: add ti,lmk04832 bindings
* clk-stm:
clk: stm32mp1: new compatible for secure RCC support
dt-bindings: clock: stm32mp1 new compatible for secure rcc
dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15
dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15
dt-bindings: clock: add IDs for SCMI clocks on stm32mp15
reset: stm32mp1: remove stm32mp1 reset
clk: stm32mp1: move RCC reset controller into RCC clock driver
clk: stm32mp1: convert to module driver
clk: stm32mp1: remove intermediate pll clocks
clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' into one clock
clk: stm32mp1: merge 'clk-hsi-div' and 'ck_hsi' into one clock
* clk-rohm:
clk: bd718xx: Drop
BD70528 support
* clk-actions:
clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoC
dt-bindings: clock: Add NIC and ETHERNET bindings for Actions S500 SoC
clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoC
clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoC
clk: actions: Fix SD clocks factor table on Owl S500 SoC
clk: actions: Fix UART clock dividers on Owl S500 SoC
* clk-ingenic:
clk: ingenic: Add support for the JZ4760
clk: ingenic: Support overriding PLLs M/N/OD calc algorithm
clk: ingenic: Remove pll_info.no_bypass_bit
clk: ingenic: Read bypass register only when there is one
clk: Support bypassing dividers
dt-bindings: clock: ingenic: Add ingenic,jz4760{,b}-cgu compatibles
The <linux/clk.h> calls support software clock gating and
thus are a key power management tool on many systems.
-----config CLKDEV_LOOKUP
----- bool
----- select HAVE_CLK
-----
config HAVE_CLK_PREPARE
bool
bool "Common Clock Framework"
depends on !HAVE_LEGACY_CLK
select HAVE_CLK_PREPARE
----- select CLKDEV_LOOKUP
+++++ select HAVE_CLK
select SRCU
select RATIONAL
help
This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
control.
+ ++++config LMK04832
+ ++++ tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner"
+ ++++ depends on SPI
+ ++++ select REGMAP_SPI
+ ++++ help
+ ++++ Say yes here to build support for Texas Instruments' LMK04832 Ultra
+ ++++ Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
+ ++++
config COMMON_CLK_MAX77686
tristate "Clock driver for Maxim 77620/77686/77802 MFD"
depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
help
Support for stm32mp157 SoC family clocks
++ +++config COMMON_CLK_STM32MP157_SCMI
++ +++ bool "stm32mp157 Clock driver with Trusted Firmware"
++ +++ depends on COMMON_CLK_STM32MP157
++ +++ select COMMON_CLK_SCMI
++ +++ select ARM_SCMI_PROTOCOL
++ +++ default y
++ +++ help
++ +++ Support for stm32mp157 SoC family clocks with Trusted Firmware using
++ +++ SCMI protocol.
++ +++
config COMMON_CLK_STM32F
def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)
help
config COMMON_CLK_BD718XX
tristate "Clock driver for 32K clk gates on ROHM PMICs"
--- -- depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528 || MFD_ROHM_BD71828
+++ ++ depends on MFD_ROHM_BD718XX || MFD_ROHM_BD71828
help
--- -- This driver supports ROHM BD71837, ROHM BD71847, ROHM BD71828 and
--- -- ROHM BD70528 PMICs clock gates.
+++ ++ This driver supports ROHM BD71837, BD71847, BD71850, BD71815
+++ ++ and BD71828 PMICs clock gates.
config COMMON_CLK_FIXED_MMIO
bool "Clock driver for Memory Mapped Fixed values"
# SPDX-License-Identifier: GPL-2.0
# common clock types
-----obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-bulk.o
-----obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
+++++obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-bulk.o clkdev.o
obj-$(CONFIG_COMMON_CLK) += clk.o
obj-$(CONFIG_COMMON_CLK) += clk-divider.o
obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
obj-$(CONFIG_COMMON_CLK_K210) += clk-k210.o
+ ++++obj-$(CONFIG_LMK04832) += clk-lmk04832.o
obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o