Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
rsr a2, interrupt
assert eqi, a2, 0
- movi a2, 0x40
+ movi a2, 1 << XCHAL_TIMER0_INTERRUPT
wsr a2, intenable
rsil a2, 0
loop a3, 1f
rsync
rsr a2, interrupt
assert eqi, a2, 0
- movi a2, 0x400
+ movi a2, 1 << XCHAL_TIMER1_INTERRUPT
wsr a2, intenable
rsil a2, 2
loop a3, 1f
rsync
rsr a2, interrupt
assert eqi, a2, 0
- movi a2, 0x2000
+ movi a2, 1 << XCHAL_TIMER2_INTERRUPT
wsr a2, intenable
rsil a2, 4
loop a3, 1f
rsr a2, interrupt
assert eqi, a2, 0
- movi a2, 0x40
+ movi a2, 1 << XCHAL_TIMER0_INTERRUPT
wsr a2, intenable
rsil a2, 0
loop a3, 1f
rsr a2, interrupt
assert eqi, a2, 0
- movi a2, 0x40
+ movi a2, 1 << XCHAL_TIMER0_INTERRUPT
wsr a2, intenable
waiti 0
test_fail