NI660X_NUM_REGS,
};
+#define NI660X_CLK_CFG_COUNTER_SWAP BIT(21)
+
#define NI660X_IO_CFG(x) (NI660X_IO_CFG_0_1 + ((x) / 2))
#define NI660X_IO_CFG_OUT_SEL(_c, _s) (((_s) & 0x3) << (((_c) % 2) ? 0 : 8))
#define NI660X_IO_CFG_OUT_SEL_MASK(_c) NI660X_IO_CFG_OUT_SEL((_c), 0x3)
[NI660X_IO_CFG_38_39] = { 0x7a2, 2 } /* read/write */
};
-/* kind of ENABLE for the second counter */
-enum clock_config_register_bits {
- CounterSwap = 0x1 << 21
-};
-
/* dma configuration register bits */
static inline unsigned dma_select_mask(unsigned dma_channel)
{
* first chip.
*/
if (chip)
- bits = CounterSwap;
+ bits = NI660X_CLK_CFG_COUNTER_SWAP;
ni_660x_write_register(dev, chip, bits, NI660X_CLK_CFG);
}