/* Macros to access registers */
-/* Interrupt overrun clear */
-#define RtdInterruptOverrunClear(dev) \
- writel(0, devpriv->las0+LAS0_OVERRUN)
-
/* Pacer counter, 24bit */
#define RtdPacerCount(dev) \
readl(devpriv->las0+LAS0_PCLK)
RtdDma0Reset(dev); /* reset onboard state */
#endif /* USE_DMA */
writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
- RtdInterruptOverrunClear(dev);
+ writel(0, devpriv->las0 + LAS0_OVERRUN);
devpriv->intCount = 0;
if (!dev->irq) { /* we need interrupts for this */
devpriv->intClearMask = ~0;
writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
readw(devpriv->las0 + LAS0_CLEAR);
- RtdInterruptOverrunClear(dev);
+ writel(0, devpriv->las0 + LAS0_OVERRUN);
writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
RtdDacClearFifo(dev, 0);