Merge branch 'mediatek-drm-fixes-2016-11-11' of https://github.com/ckhu-mediatek...

This branch include one patch to fix a typo, two patches to disable
vblank interrupt, and three patches to support HDMI 4K resolution.

* 'mediatek-drm-fixes-2016-11-11' of https://github.com/ckhu-mediatek/linux.git-tags:
  drm/mediatek: modify the factor to make the pll_rate set in the 1G-2G range
  drm/mediatek: enhance the HDMI driving current
  drm/mediatek: do mtk_hdmi_send_infoframe after HDMI clock enable
  drm/mediatek: clear IRQ status before enable OVL interrupt
  drm/mediatek: set vblank_disable_allowed to true
  drm/mediatek: fix a typo of OD_CFG to OD_RELAYMODE

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 019b7ca392d7a49db0ffcb25ccb36f293f9d530e..f75c5b5a536c7a83cac6119a1d8a255792712172 100644 (file)
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -80,6 +80,7 @@ static void mtk_ovl_enable_vblank(struct mtk_ddp_comp *comp,
                                                 ddp_comp);
 
        priv->crtc = crtc;
+       writel(0x0, comp->regs + DISP_REG_OVL_INTSTA);
        writel_relaxed(OVL_FME_CPL_INT, comp->regs + DISP_REG_OVL_INTEN);
 }
 

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 0186e500d2a544d8c90769428c7673bec1cd68c0..90fb831ef031b9794df4f1ef95609204bedce93a 100644 (file)
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -432,11 +432,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
        unsigned long pll_rate;
        unsigned int factor;
 
+       /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
        pix_rate = 1000UL * mode->clock;
-       if (mode->clock <= 74000)
+       if (mode->clock <= 27000)
+               factor = 16 * 3;
+       else if (mode->clock <= 84000)
                factor = 8 * 3;
-       else
+       else if (mode->clock <= 167000)
                factor = 4 * 3;
+       else
+               factor = 2 * 3;
        pll_rate = pix_rate * factor;
 
        dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index df33b3ca6ffd5b2038e3e01d81ada28ffd33462e..aa5f20fabd10f4f650411ac94d9e7b01a4ddf33a 100644 (file)
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -123,7 +123,7 @@ static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
                          unsigned int bpc)
 {
        writel(w << 16 | h, comp->regs + DISP_OD_SIZE);
-       writel(OD_RELAYMODE, comp->regs + OD_RELAYMODE);
+       writel(OD_RELAYMODE, comp->regs + OD_CFG);
        mtk_dither_set(comp, bpc, DISP_OD_CFG);
 }
 

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index cf83f6507ec8211566f87cbf4878e5d76c3eff0b..0b2ae47eb52ca7728c6c17301262acdae6310b4e 100644 (file)
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -217,6 +217,7 @@ static int mtk_drm_kms_init(struct drm_device *drm)
        if (ret < 0)
                goto err_component_unbind;
 
+       drm->vblank_disable_allowed = true;
        drm_kms_helper_poll_init(drm);
        drm_mode_config_reset(drm);
 

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 71227deef21b1ea96d6a2594b98a584d41ad6320..0e8c4d9af34069f55e8784d8e43b6e4e56251cfa 100644 (file)
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1133,12 +1133,6 @@ static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
        phy_power_on(hdmi->phy);
        mtk_hdmi_aud_output_config(hdmi, mode);
 
-       mtk_hdmi_setup_audio_infoframe(hdmi);
-       mtk_hdmi_setup_avi_infoframe(hdmi, mode);
-       mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
-       if (mode->flags & DRM_MODE_FLAG_3D_MASK)
-               mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
-
        mtk_hdmi_hw_vid_black(hdmi, false);
        mtk_hdmi_hw_aud_unmute(hdmi);
        mtk_hdmi_hw_send_av_unmute(hdmi);
@@ -1401,6 +1395,16 @@ static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
        hdmi->powered = true;
 }
 
+static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
+                                   struct drm_display_mode *mode)
+{
+       mtk_hdmi_setup_audio_infoframe(hdmi);
+       mtk_hdmi_setup_avi_infoframe(hdmi, mode);
+       mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
+       if (mode->flags & DRM_MODE_FLAG_3D_MASK)
+               mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
+}
+
 static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge)
 {
        struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
@@ -1409,6 +1413,7 @@ static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge)
        clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
        clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
        phy_power_on(hdmi->phy);
+       mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
 
        hdmi->enabled = true;
 }

diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
index 8a24754b440f06585ec67bda44a182cc34e00c84..51cb9cfb6646e3f46a63a2073b923ef6b3f02b2d 100644 (file)
--- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
@@ -265,6 +265,9 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
        struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
        unsigned int pre_div;
        unsigned int div;
+       unsigned int pre_ibias;
+       unsigned int hdmi_ibias;
+       unsigned int imp_en;
 
        dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__,
                rate, parent_rate);
@@ -298,18 +301,31 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
                          (0x1 << PLL_BR_SHIFT),
                          RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
                          RG_HDMITX_PLL_BR);
-       mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
+       if (rate < 165000000) {
+               mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
+                                       RG_HDMITX_PRD_IMP_EN);
+               pre_ibias = 0x3;
+               imp_en = 0x0;
+               hdmi_ibias = hdmi_phy->ibias;
+       } else {
+               mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
+                                     RG_HDMITX_PRD_IMP_EN);
+               pre_ibias = 0x6;
+               imp_en = 0xf;
+               hdmi_ibias = hdmi_phy->ibias_up;
+       }
        mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
-                         (0x3 << PRD_IBIAS_CLK_SHIFT) |
-                         (0x3 << PRD_IBIAS_D2_SHIFT) |
-                         (0x3 << PRD_IBIAS_D1_SHIFT) |
-                         (0x3 << PRD_IBIAS_D0_SHIFT),
+                         (pre_ibias << PRD_IBIAS_CLK_SHIFT) |
+                         (pre_ibias << PRD_IBIAS_D2_SHIFT) |
+                         (pre_ibias << PRD_IBIAS_D1_SHIFT) |
+                         (pre_ibias << PRD_IBIAS_D0_SHIFT),
                          RG_HDMITX_PRD_IBIAS_CLK |
                          RG_HDMITX_PRD_IBIAS_D2 |
                          RG_HDMITX_PRD_IBIAS_D1 |
                          RG_HDMITX_PRD_IBIAS_D0);
        mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
-                         (0x0 << DRV_IMP_EN_SHIFT), RG_HDMITX_DRV_IMP_EN);
+                         (imp_en << DRV_IMP_EN_SHIFT),
+                         RG_HDMITX_DRV_IMP_EN);
        mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
                          (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
                          (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
@@ -318,12 +334,14 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
                          RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
                          RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
        mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
-                         (hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) |
-                         (hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) |
-                         (hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) |
-                         (hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT),
-                         RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 |
-                         RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0);
+                         (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) |
+                         (hdmi_ibias << DRV_IBIAS_D2_SHIFT) |
+                         (hdmi_ibias << DRV_IBIAS_D1_SHIFT) |
+                         (hdmi_ibias << DRV_IBIAS_D0_SHIFT),
+                         RG_HDMITX_DRV_IBIAS_CLK |
+                         RG_HDMITX_DRV_IBIAS_D2 |
+                         RG_HDMITX_DRV_IBIAS_D1 |
+                         RG_HDMITX_DRV_IBIAS_D0);
        return 0;
 }