void op_mtc0_context (void)
{
- env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & ~0x007FFFFF);
+ env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
RETURN();
}
RETURN();
}
-void op_mtc0_xcontext (void)
-{
- env->CP0_XContext = (int32_t)T0; /* XXX */
- RETURN();
-}
-
void op_mtc0_framemask (void)
{
env->CP0_Framemask = T0; /* XXX */
RETURN();
}
+#ifdef TARGET_MIPS64
void op_dmfc0_entrylo0 (void)
{
T0 = env->CP0_EntryLo0;
void op_dmtc0_context (void)
{
- env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
+ env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
RETURN();
}
void op_dmtc0_xcontext (void)
{
- env->CP0_XContext = T0; /* XXX */
+ env->CP0_XContext = (env->CP0_XContext & 0xffffffff) | (T0 & ~0xffffffff);
RETURN();
}
env->CP0_ErrorEPC = T0;
RETURN();
}
+#endif /* TARGET_MIPS64 */
#if 0
# define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
switch (sel) {
case 0:
/* 64 bit MMU only */
- gen_op_mtc0_xcontext();
+ /* Nothing writable in lower 32 bits */
rn = "XContext";
break;
default:
generate_exception(ctx, EXCP_RI);
}
+#ifdef TARGET_MIPS64
static void gen_dmfc0 (DisasContext *ctx, int reg, int sel)
{
const char *rn = "invalid";
#endif
generate_exception(ctx, EXCP_RI);
}
+#endif /* TARGET_MIPS64 */
static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
{
gen_mtc0(ctx, rd, ctx->opcode & 0x7);
opn = "mtc0";
break;
+#ifdef TARGET_MIPS64
case OPC_DMFC0:
if (rt == 0) {
/* Treat as NOP */
gen_dmtc0(ctx, rd, ctx->opcode & 0x7);
opn = "dmtc0";
break;
+#endif
#if defined(MIPS_USES_R4K_TLB)
case OPC_TLBWI:
gen_op_tlbwi();