drm/tegra: sor: Reset during initialization

As there isn't a way for the firmware on the Nyan Chromebooks to hand
over the display to the kernel, and the kernel isn't redoing the whole
configuration at present.

With this patch, the SOR is brought to a known state and we get correct
display on every boot.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index 41c5a6ed2c367b8f7f4e216e8554581ae457841a..7591d8901f9a24ddd61d035500116c617e4df3f6 100644 (file)
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -1512,12 +1512,30 @@ static int tegra_sor_init(struct host1x_client *client)
                }
        }
 
+       /*
+        * XXX: Remove this reset once proper hand-over from firmware to
+        * kernel is possible.
+        */
+       err = reset_control_assert(sor->rst);
+       if (err < 0) {
+               dev_err(sor->dev, "failed to assert SOR reset: %d\n", err);
+               return err;
+       }
+
        err = clk_prepare_enable(sor->clk);
        if (err < 0) {
                dev_err(sor->dev, "failed to enable clock: %d\n", err);
                return err;
        }
 
+       usleep_range(1000, 3000);
+
+       err = reset_control_deassert(sor->rst);
+       if (err < 0) {
+               dev_err(sor->dev, "failed to deassert SOR reset: %d\n", err);
+               return err;
+       }
+
        err = clk_prepare_enable(sor->clk_safe);
        if (err < 0)
                return err;