drm/amd/display: Implement fixed DP drive settings

[Why]
Currently there are use cases that require DP link to maintain fixed VS
and PE in HW regardless of what the sink requests. BIOS integrated info
table will specify whether we need to use the fixed drive settings, and
the drive settings to use.

[How]
Implement changes to parse the integrated info table and set the fixed
drive settings accordingly.

Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Agustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index c17732fba0394dae38779e37ef2fe7ca9c5d73c0..a4bef4364afd8d65688ba400c3c84a0aa6d683c6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -2321,6 +2321,8 @@ static enum bp_result get_integrated_info_v2_2(
 
        info->ext_disp_conn_info.checksum =
                info_v2_2->extdispconninfo.checksum;
+       info->ext_disp_conn_info.fixdpvoltageswing =
+               info_v2_2->extdispconninfo.fixdpvoltageswing;
 
        info->edp1_info.edp_backlight_pwm_hz =
        le16_to_cpu(info_v2_2->edp1_info.edp_backlight_pwm_hz);

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 96d2001ede61300d5f738ad6e704fd3a3ef32b54..a1fa50ddf43e5953107fae8575b0f85d1495213c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1660,6 +1660,14 @@ static bool dc_link_construct_legacy(struct dc_link *link,
                                DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
                                DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
                        }
+
+                       if (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) {
+                               link->bios_forced_drive_settings.VOLTAGE_SWING =
+                                               (info->ext_disp_conn_info.fixdpvoltageswing & 0x3);
+                               link->bios_forced_drive_settings.PRE_EMPHASIS =
+                                               ((info->ext_disp_conn_info.fixdpvoltageswing >> 2) & 0x3);
+                       }
+
                        break;
                }
        }

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index e514506b199752c37ca3bf3cec21beb37ae9552e..3313f2af139ff9ba33088852362a58565a7444ba 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1661,7 +1661,13 @@ static void override_training_settings(
        if (overrides->ffe_preset != NULL)
                lt_settings->ffe_preset = overrides->ffe_preset;
 #endif
-
+       /* Override HW lane settings with BIOS forced values if present */
+       if (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN &&
+                       link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
+               lt_settings->voltage_swing = &link->bios_forced_drive_settings.VOLTAGE_SWING;
+               lt_settings->pre_emphasis = &link->bios_forced_drive_settings.PRE_EMPHASIS;
+               lt_settings->always_match_dpcd_with_hw_lane_settings = false;
+       }
        for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
                lt_settings->lane_settings[lane].VOLTAGE_SWING =
                        lt_settings->voltage_swing != NULL ?

diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 8902d642e719a4080461c7f4d3c1225136303f77..517950674729af4d7dd53cb6f753957d95fda857 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -178,6 +178,9 @@ struct dc_link {
 
        struct psr_settings psr_settings;
 
+       /* Drive settings read from integrated info table */
+       struct dc_lane_settings bios_forced_drive_settings;
+
        /* MST record stream using this link */
        struct link_flags {
                bool dp_keep_receiver_powered;

diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
index 792652236c61bb6c8cae3f37fe3b067e3054f7f5..dd974c428d23d6b492e4c1383bdde424bd97056a 100644 (file)
--- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
+++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
@@ -328,6 +328,7 @@ struct integrated_info {
 
                uint8_t gu_id[NUMBER_OF_UCHAR_FOR_GUID];
                uint8_t checksum;
+               uint8_t fixdpvoltageswing;
        } ext_disp_conn_info; /* exiting long long time */
 
        struct available_s_clk_list {

diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
index 9ffea7b405454c465c1f8d1971355f325dddba7b..9a16fc8552542429c00a872742b771ac17b69c8e 100644 (file)
--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
@@ -117,6 +117,12 @@ struct link_training_settings {
        bool enhanced_framing;
        bool allow_invalid_msa_timing_param;
        enum lttpr_mode lttpr_mode;
+
+       /* disallow different lanes to have different lane settings */
+       bool disallow_per_lane_settings;
+       /* dpcd lane settings will always use the same hw lane settings
+        * even if it doesn't match requested lane adjust */
+       bool always_match_dpcd_with_hw_lane_settings;
 };
 
 /*TODO: Move this enum test harness*/