drm/i915/chv: Add CHV HW status to SSEU status

Collect the currently enabled counts of slice, subslice, and
execution units using the power gate control ack message
registers specific to Cherryview.

Slice/subslice/EU info and hardware status can now be
determined for CHV, so allow the debugfs SSEU status dump
to proceed for CHV devices.

Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3f647865653d3e9b06511745335c7b23fc7b7cd6..f293caf74dc77d53a2ca9f1e855672a24182fa79 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4459,7 +4459,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
        struct drm_i915_private *dev_priv = dev->dev_private;
        unsigned int s_tot = 0, ss_tot = 0, ss_per = 0, eu_tot = 0, eu_per = 0;
 
-       if (INTEL_INFO(dev)->gen < 9)
+       if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
                return -ENODEV;
 
        seq_puts(m, "SSEU Device Info\n");
@@ -4481,7 +4481,34 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
                   yesno(INTEL_INFO(dev)->has_eu_pg));
 
        seq_puts(m, "SSEU Device Status\n");
-       if (IS_SKYLAKE(dev)) {
+       if (IS_CHERRYVIEW(dev)) {
+               const int ss_max = 2;
+               int ss;
+               u32 sig1[ss_max], sig2[ss_max];
+
+               sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
+               sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
+               sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
+               sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
+
+               for (ss = 0; ss < ss_max; ss++) {
+                       unsigned int eu_cnt;
+
+                       if (sig1[ss] & CHV_SS_PG_ENABLE)
+                               /* skip disabled subslice */
+                               continue;
+
+                       s_tot = 1;
+                       ss_per++;
+                       eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
+                                ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
+                                ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
+                                ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
+                       eu_tot += eu_cnt;
+                       eu_per = max(eu_per, eu_cnt);
+               }
+               ss_tot = ss_per;
+       } else if (IS_SKYLAKE(dev)) {
                const int s_max = 3, ss_max = 4;
                int s, ss;
                u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f680f4d5e31fa258195f67b0d7abeac2163bc8d4..f700922bcb569e628ad86ddd4d212c70b1031a35 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6226,6 +6226,17 @@ enum skl_disp_power_wells {
 #define   GEN6_RC6                     3
 #define   GEN6_RC7                     4
 
+#define CHV_POWER_SS0_SIG1             0xa720
+#define CHV_POWER_SS1_SIG1             0xa728
+#define   CHV_SS_PG_ENABLE             (1<<1)
+#define   CHV_EU08_PG_ENABLE           (1<<9)
+#define   CHV_EU19_PG_ENABLE           (1<<17)
+#define   CHV_EU210_PG_ENABLE          (1<<25)
+
+#define CHV_POWER_SS0_SIG2             0xa724
+#define CHV_POWER_SS1_SIG2             0xa72c
+#define   CHV_EU311_PG_ENABLE          (1<<1)
+
 #define GEN9_SLICE0_PGCTL_ACK          0x804c
 #define GEN9_SLICE1_PGCTL_ACK          0x8050
 #define GEN9_SLICE2_PGCTL_ACK          0x8054