drm/amd/display: Support CW4 for DMUB ringbuffer inbox

[Why]
Region 4 is non cacheable and slower than using cache window 4.

[How]
Check the firmware version to determine how we should program the
base address and memory windows.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
index edc73d6d7ba2848cb8a779a292a86dea8af9df23..1e03f6fdabd6c4080f4b4255200165eea6365adb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
@@ -215,11 +215,22 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
        /* TODO: Move this to CW4. */
        dmub_dcn20_translate_addr(&cw4->offset, fb_base, fb_offset, &offset);
 
-       REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
-       REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
-       REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS,
-                 cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE,
-                 1);
+       /* New firmware can support CW4. */
+       if (dmub->fw_version > DMUB_FW_VERSION(1, 0, 10)) {
+               REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
+               REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
+               REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
+               REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
+                         DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
+                         DMCUB_REGION3_CW4_ENABLE, 1);
+       } else {
+               REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
+               REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
+               REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0,
+                         DMCUB_REGION4_TOP_ADDRESS,
+                         cw4->region.top - cw4->region.base - 1,
+                         DMCUB_REGION4_ENABLE, 1);
+       }
 
        dmub_dcn20_translate_addr(&cw5->offset, fb_base, fb_offset, &offset);
 
@@ -243,9 +254,12 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
 void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
                              const struct dmub_region *inbox1)
 {
-       /* TODO: Use CW4 instead of region 4. */
+       /* New firmware can support CW4 for the inbox. */
+       if (dmub->fw_version > DMUB_FW_VERSION(1, 0, 10))
+               REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
+       else
+               REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000);
 
-       REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000);
        REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
 }
 

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 3559093027ee3aadbf6b3e538e190d8c27427a9e..d128b0639572184b7348ffdf1506aa1ebdb94201 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -62,6 +62,7 @@
 #define DMUB_CW0_BASE (0x60000000)
 #define DMUB_CW1_BASE (0x61000000)
 #define DMUB_CW3_BASE (0x63000000)
+#define DMUB_CW4_BASE (0x64000000)
 #define DMUB_CW5_BASE (0x65000000)
 #define DMUB_CW6_BASE (0x66000000)
 
@@ -403,7 +404,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
                cw3.region.top = cw3.region.base + bios_fb->size;
 
                cw4.offset.quad_part = mail_fb->gpu_addr;
-               cw4.region.base = cw3.region.top + 1;
+               cw4.region.base = DMUB_CW4_BASE;
                cw4.region.top = cw4.region.base + mail_fb->size;
 
                inbox1.base = cw4.region.base;