dcn10_power_on_fe(dc, pipe_ctx, context);
/* temporary dcn1 wa:
- * watermark update requires toggle after a/b/c/d sets are programmed
- * if hubp is pg then wm value doesn't get properaged to hubp
- * need to toggle after ungate to ensure wm gets to hubp.
- *
- * final solution: we need to get SMU to do the toggle as
- * DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we should have
- * both driver and fw accessing same register
- */
+ * watermark update requires toggle after a/b/c/d sets are programmed
+ * if hubp is pg then wm value doesn't get properaged to hubp
+ * need to toggle after ungate to ensure wm gets to hubp.
+ *
+ * final solution: we need to get SMU to do the toggle as
+ * DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we should have
+ * both driver and fw accessing same register
+ */
toggle_watermark_change_req(dc->hwseq);
update_dchubp_dpp(dc, pipe_ctx, context);
}
static void min_set_viewport(
- struct mem_input *mem_input,
- const struct rect *viewport,
- const struct rect *viewport_c)
+ struct mem_input *mem_input,
+ const struct rect *viewport,
+ const struct rect *viewport_c)
{
struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
- REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
- PRI_VIEWPORT_WIDTH, viewport->width,
- PRI_VIEWPORT_HEIGHT, viewport->height);
+ REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
+ PRI_VIEWPORT_WIDTH, viewport->width,
+ PRI_VIEWPORT_HEIGHT, viewport->height);
- REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
- PRI_VIEWPORT_X_START, viewport->x,
- PRI_VIEWPORT_Y_START, viewport->y);
+ REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
+ PRI_VIEWPORT_X_START, viewport->x,
+ PRI_VIEWPORT_Y_START, viewport->y);
- /*for stereo*/
- REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
- SEC_VIEWPORT_WIDTH, viewport->width,
- SEC_VIEWPORT_HEIGHT, viewport->height);
+ /*for stereo*/
+ REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
+ SEC_VIEWPORT_WIDTH, viewport->width,
+ SEC_VIEWPORT_HEIGHT, viewport->height);
- REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
- SEC_VIEWPORT_X_START, viewport->x,
- SEC_VIEWPORT_Y_START, viewport->y);
+ REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
+ SEC_VIEWPORT_X_START, viewport->x,
+ SEC_VIEWPORT_Y_START, viewport->y);
- /* DC supports NV12 only at the moment */
- REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
- PRI_VIEWPORT_WIDTH_C, viewport_c->width,
- PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
+ /* DC supports NV12 only at the moment */
+ REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
+ PRI_VIEWPORT_WIDTH_C, viewport_c->width,
+ PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
- REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
- PRI_VIEWPORT_X_START_C, viewport_c->x,
- PRI_VIEWPORT_Y_START_C, viewport_c->y);
+ REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
+ PRI_VIEWPORT_X_START_C, viewport_c->x,
+ PRI_VIEWPORT_Y_START_C, viewport_c->y);
}
void dcn10_mem_input_read_state(struct dcn10_mem_input *mi,
};
struct step_and_delay_info {
- uint32_t step;
- uint32_t delay;
- uint32_t recommended_ref_div;
+ uint32_t step;
+ uint32_t delay;
+ uint32_t recommended_ref_div;
};
struct spread_spectrum_info {
#define NUMBER_OF_AVAILABLE_SCLK 5
struct i2c_reg_info {
- unsigned char i2c_reg_index;
- unsigned char i2c_reg_val;
+ unsigned char i2c_reg_index;
+ unsigned char i2c_reg_val;
};
struct ext_hdmi_settings {
- unsigned char slv_addr;
- unsigned char reg_num;
- struct i2c_reg_info reg_settings[9];
- unsigned char reg_num_6g;
- struct i2c_reg_info reg_settings_6g[3];
+ unsigned char slv_addr;
+ unsigned char reg_num;
+ struct i2c_reg_info reg_settings[9];
+ unsigned char reg_num_6g;
+ struct i2c_reg_info reg_settings_6g[3];
};