]> git.proxmox.com Git - mirror_ubuntu-kernels.git/commitdiff
thermal: exynos: Add support for many TRIMINFO_CTRL registers
authorChanwoo Choi <cw00.choi@samsung.com>
Wed, 3 Sep 2014 03:09:02 +0000 (12:09 +0900)
committerEduardo Valentin <edubezval@gmail.com>
Mon, 3 Nov 2014 03:02:48 +0000 (23:02 -0400)
This patch support many TRIMINFO_CTRL registers if specific Exynos SoC
has one more TRIMINFO_CTRL registers. Also this patch uses proper 'RELOAD'
shift/mask bit operation to set RELOAD feature instead of static value.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: Amit Daniel Kachhap <amit.daniel@samsung.com>
Reviewed-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
drivers/thermal/samsung/exynos_thermal_common.h
drivers/thermal/samsung/exynos_tmu.c
drivers/thermal/samsung/exynos_tmu.h
drivers/thermal/samsung/exynos_tmu_data.c
drivers/thermal/samsung/exynos_tmu_data.h

index cd4471925cddbacb95b2c0404625f94264ef3a20..158f5aa8dc5d105289e0d1b4b792fc6b28f53a83 100644 (file)
@@ -27,6 +27,7 @@
 #define SENSOR_NAME_LEN        16
 #define MAX_TRIP_COUNT 8
 #define MAX_COOLING_DEVICE 4
+#define MAX_TRIMINFO_CTRL_REG  2
 
 #define ACTIVE_INTERVAL 500
 #define IDLE_INTERVAL 10000
index 35437dffaecc1ec21b2fcca7e4dcbb4ac0191a18..092ab69d6282f2ba1da62a5b843b29d40c366261 100644 (file)
@@ -127,7 +127,7 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
        struct exynos_tmu_data *data = platform_get_drvdata(pdev);
        struct exynos_tmu_platform_data *pdata = data->pdata;
        const struct exynos_tmu_registers *reg = pdata->registers;
-       unsigned int status, trim_info = 0, con;
+       unsigned int status, trim_info = 0, con, ctrl;
        unsigned int rising_threshold = 0, falling_threshold = 0;
        int ret = 0, threshold_code, i;
 
@@ -144,8 +144,17 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
                }
        }
 
-       if (TMU_SUPPORTS(pdata, TRIM_RELOAD))
-               __raw_writel(1, data->base + reg->triminfo_ctrl);
+       if (TMU_SUPPORTS(pdata, TRIM_RELOAD)) {
+               for (i = 0; i < reg->triminfo_ctrl_count; i++) {
+                       if (pdata->triminfo_reload[i]) {
+                               ctrl = readl(data->base +
+                                               reg->triminfo_ctrl[i]);
+                               ctrl |= pdata->triminfo_reload[i];
+                               writel(ctrl, data->base +
+                                               reg->triminfo_ctrl[i]);
+                       }
+               }
+       }
 
        /* Save trimming info in order to perform calibration */
        if (data->soc == SOC_ARCH_EXYNOS5440) {
index d503f35e3cd977eeea04097f8489f02cc9465ee8..f67203bfd83c021a7e253af59666b6795b2d4a72 100644 (file)
@@ -78,6 +78,7 @@ enum soc_type {
  * slightly across different exynos SOC's.
  * @triminfo_data: register containing 2 pont trimming data
  * @triminfo_ctrl: trim info controller register.
+ * @triminfo_ctrl_count: the number of trim info controller register.
  * @tmu_ctrl: TMU main controller register.
  * @test_mux_addr_shift: shift bits of test mux address.
  * @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register.
@@ -112,8 +113,8 @@ enum soc_type {
 struct exynos_tmu_registers {
        u32     triminfo_data;
 
-       u32     triminfo_ctrl;
-       u32     triminfo_ctrl1;
+       u32     triminfo_ctrl[MAX_TRIMINFO_CTRL_REG];
+       u32     triminfo_ctrl_count;
 
        u32     tmu_ctrl;
        u32     test_mux_addr_shift;
@@ -200,6 +201,7 @@ struct exynos_tmu_registers {
  * @second_point_trim: temp value of the second point trimming
  * @default_temp_offset: default temperature offset in case of no trimming
  * @test_mux; information if SoC supports test MUX
+ * @triminfo_reload: reload value to read TRIMINFO register
  * @cal_type: calibration type for temperature
  * @freq_clip_table: Table representing frequency reduction percentage.
  * @freq_tab_count: Count of the above table as frequency reduction may
@@ -230,6 +232,7 @@ struct exynos_tmu_platform_data {
        u8 second_point_trim;
        u8 default_temp_offset;
        u8 test_mux;
+       u8 triminfo_reload[MAX_TRIMINFO_CTRL_REG];
 
        enum calibration_type cal_type;
        enum soc_type type;
index 177ada5846cdc46693f9a12e14d198b6b7e0b7d8..362a1e1485515d6ed84a6e4d4a96063847ea036c 100644 (file)
@@ -169,7 +169,8 @@ struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
 #if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
 static const struct exynos_tmu_registers exynos4412_tmu_registers = {
        .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
-       .triminfo_ctrl = EXYNOS_TMU_TRIMINFO_CON,
+       .triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON,
+       .triminfo_ctrl_count = 1,
        .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
        .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
        .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
@@ -231,6 +232,7 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
                .temp_level = 95, \
        }, \
        .freq_tab_count = 2, \
+       .triminfo_reload[0] = EXYNOS_TRIMINFO_RELOAD_ENABLE, \
        .registers = &exynos4412_tmu_registers, \
        .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
                        TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
index ac03b76c51ccfae3f1cac48735031885787c97d2..6b47a174c8fa03d46c1e45f6c286f534533a3bfb 100644 (file)
@@ -51,6 +51,7 @@
 #define EXYNOS_THD_TEMP_FALL           0x54
 #define EXYNOS_EMUL_CON                0x80
 
+#define EXYNOS_TRIMINFO_RELOAD_ENABLE  1
 #define EXYNOS_TRIMINFO_25_SHIFT       0
 #define EXYNOS_TRIMINFO_85_SHIFT       8
 #define EXYNOS_TMU_RISE_INT_MASK       0x111