ARM: dts: hisilicon: Align L2 cache-controller nodename with dtschema

Fix dtschema validator warnings like:
    l2-cache: $nodename:0: 'l2-cache' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index 9c207a690df5033c26daf990be1ceb81b4162554..f0af1bf2b4d8eb51bf511b25f0fe000a1439c974 100644 (file)
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -71,7 +71,7 @@
                interrupt-parent = <&gic>;
                ranges = <0 0xfc000000 0x2000000>;
 
-               L2: l2-cache {
+               L2: cache-controller {
                        compatible = "arm,pl310-cache";
                        reg = <0x100000 0x100000>;
                        interrupts = <0 15 4>;

diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index 696e6982a688b2c89e97b9a55a1af30b129b66eb..3ee7967c202d5b4c5ab6b552ca11a98a1bd9838c 100644 (file)
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -381,7 +381,7 @@
                        interrupts = <1 13 0xf01>;
                };
 
-               l2: l2-cache {
+               l2: cache-controller {
                        compatible = "arm,pl310-cache";
                        reg = <0x00a10000 0x100000>;
                        interrupts = <0 15 4>;