drm/admgpu: move XDMA golden registers to dce code

Already moved other display registers.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 926c8e0789b0ced696ec078b0ddd3c1d820a54f3..192dfe55b9ab31771eb793c9cd8bcd772a87a988 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -120,10 +120,19 @@ static const u32 golden_settings_tonga_a11[] =
        mmHDMI_CONTROL, 0x31000111, 0x00000011,
 };
 
+static const u32 tonga_mgcg_cgcg_init[] =
+{
+       mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
+       mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
+};
+
 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
 {
        switch (adev->asic_type) {
        case CHIP_TONGA:
+               amdgpu_program_register_sequence(adev,
+                                                tonga_mgcg_cgcg_init,
+                                                (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 golden_settings_tonga_a11,
                                                 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index bc60fd1844f325d0f88152e6b64c8ce31f93f99a..a530c5dd11936f1b0128944a64e5df66b65db530 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -120,10 +120,19 @@ static const u32 cz_golden_settings_a11[] =
        mmFBC_MISC, 0x1f311fff, 0x14300000,
 };
 
+static const u32 cz_mgcg_cgcg_init[] =
+{
+       mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
+       mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
+};
+
 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
 {
        switch (adev->asic_type) {
        case CHIP_CARRIZO:
+               amdgpu_program_register_sequence(adev,
+                                                cz_mgcg_cgcg_init,
+                                                (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
                amdgpu_program_register_sequence(adev,
                                                 cz_golden_settings_a11,
                                                 (const u32)ARRAY_SIZE(cz_golden_settings_a11));

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index be7c176106962becdd8cbc1d72c5fa231a58d747..b71f41412f9152ea3eb6b8078535cc4bd4ae9d9e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -173,8 +173,6 @@ static const u32 tonga_mgcg_cgcg_init[] =
        mmPCIE_DATA, 0x000f0000, 0x00000000,
        mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
        mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
-       mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
-       mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
        mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
        mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 };
@@ -193,8 +191,6 @@ static const u32 cz_mgcg_cgcg_init[] =
        mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
        mmPCIE_INDEX, 0xffffffff, 0x0140001c,
        mmPCIE_DATA, 0x000f0000, 0x00000000,
-       mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
-       mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
        mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
        mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 };